[PATCH 2/6] net/idpf: fix DD bit byte offset in split queue AVX2 Rx

[Shaiq Wani]

The split queue completion descriptor (virtchnl2_rx_flex_desc_adv_nic_3)
has two distinct status fields: status_err0_qw0 at byte offset 1 and
status_err0_qw1 at byte offset 8.  The DD (descriptor done) bit lives
in status_err0_qw1 (byte 8), not status_err0_qw0 (byte 1).

Byte 1 (status_err0_qw0) bit 0 is the LPBK (loopback) indicator, so
reading DD from byte 1 checks the wrong field entirely.

Fix the _mm_extract_epi8 index from 1 to 8 so the code reads the DD
bit from its correct location in the writeback descriptor.

Fixes: 1f065f9d75ff ("net/idpf: add AVX2 Rx path for split queue config")
Signed-off-by: Shaiq Wani <shaiq.wani at intel.com>
---
 drivers/net/intel/idpf/idpf_common_rxtx_avx2.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/intel/idpf/idpf_common_rxtx_avx2.c b/drivers/net/intel/idpf/idpf_common_rxtx_avx2.c
index cd10c27a30..28d4246134 100644
--- a/drivers/net/intel/idpf/idpf_common_rxtx_avx2.c
+++ b/drivers/net/intel/idpf/idpf_common_rxtx_avx2.c
@@ -587,11 +587,11 @@ idpf_dp_splitq_recv_pkts_avx2(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_
 		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data, rearm2);
 		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data, rearm3);
 
-		/* Extract DD and generation bits from the already-loaded descriptor data (d0-d3) */
-		stat0 = (uint8_t)_mm_extract_epi8(d0, 1);
-		stat1 = (uint8_t)_mm_extract_epi8(d1, 1);
-		stat2 = (uint8_t)_mm_extract_epi8(d2, 1);
-		stat3 = (uint8_t)_mm_extract_epi8(d3, 1);
+		/* Extract DD bit from status_err0_qw1 (byte 8 of descriptor) */
+		stat0 = (uint8_t)_mm_extract_epi8(d0, 8);
+		stat1 = (uint8_t)_mm_extract_epi8(d1, 8);
+		stat2 = (uint8_t)_mm_extract_epi8(d2, 8);
+		stat3 = (uint8_t)_mm_extract_epi8(d3, 8);
 
 		pktlen_gen0 = (uint16_t)_mm_extract_epi16(d0, 2);
 		pktlen_gen1 = (uint16_t)_mm_extract_epi16(d1, 2);
-- 
2.34.1