[PATCH 4/6] net/idpf: fix ptype insert position in split queue AVX2 Rx

[Shaiq Wani]

The __m256i register mb10 holds rearm data for two mbufs: mbuf 0 in
the low 128-bit lane (dwords 0-3) and mbuf 1 in the high 128-bit
lane (dwords 4-7).  The packet_type field sits at dword 0 within
each mbuf's rearm_data layout.

For mbuf 1 (high lane), the packet_type must be inserted at
_mm256_insert_epi32 index 4 (first dword of the high 128-bit lane).
Index 2 is the third dword of the low lane, which overwrites the
wrong mbuf's data.  The same applies to mb32 for mbuf 3.

Fixes: 1f065f9d75ff ("net/idpf: add AVX2 Rx path for split queue config")
Signed-off-by: Shaiq Wani <shaiq.wani at intel.com>
---
 drivers/net/intel/idpf/idpf_common_rxtx_avx2.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/intel/idpf/idpf_common_rxtx_avx2.c b/drivers/net/intel/idpf/idpf_common_rxtx_avx2.c
index d3a8e17778..e66dcc7a14 100644
--- a/drivers/net/intel/idpf/idpf_common_rxtx_avx2.c
+++ b/drivers/net/intel/idpf/idpf_common_rxtx_avx2.c
@@ -570,9 +570,9 @@ idpf_dp_splitq_recv_pkts_avx2(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_
 		ptype2 = (uint16_t)_mm256_extract_epi16(pt32, 1);
 		ptype3 = (uint16_t)_mm256_extract_epi16(pt32, 9);
 
-		mb10 = _mm256_insert_epi32(mb10, (int)ptype_tbl[ptype1], 2);
+		mb10 = _mm256_insert_epi32(mb10, (int)ptype_tbl[ptype1], 4);
 		mb10 = _mm256_insert_epi32(mb10, (int)ptype_tbl[ptype0], 0);
-		mb32 = _mm256_insert_epi32(mb32, (int)ptype_tbl[ptype3], 2);
+		mb32 = _mm256_insert_epi32(mb32, (int)ptype_tbl[ptype3], 4);
 		mb32 = _mm256_insert_epi32(mb32, (int)ptype_tbl[ptype2], 0);
 
 		/* Build rearm data for each mbuf */
-- 
2.34.1