[dpdk-stable] patch 'net/igb: fix LSC interrupt when using MSI-X' has been queued to stable release 18.11.1

[Kevin Traynor]

Hi,

FYI, your patch has been queued to stable release 18.11.1

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 12/18/18. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Thanks.

Kevin Traynor

---
>From c7dd7044fcf39e9bb4665fcc06d388422eaed4ef Mon Sep 17 00:00:00 2001
From: "Timmons C. Player" <timmons.player at spirent.com>
Date: Mon, 19 Nov 2018 14:48:54 +0000
Subject: [PATCH] net/igb: fix LSC interrupt when using MSI-X

[ upstream commit 7f5c81d5689d4d1b4dce8279a6eb3318bddf1607 ]

Take the 'other interrupt' into account when setting up
MSI-X interrupts and use the proper mask when enabling it.
Also, rearm the MSI-X vector after the LSC interrupt fires.

This change allows both LSC and RXQ interrupts to work at
the same time when using MSI-X interrupts.

Signed-off-by: Timmons C. Player <timmons.player at spirent.com>
Acked-by: Wei Zhao <wei.zhao1 at intel.com>
---
 drivers/net/e1000/igb_ethdev.c | 43 +++++++++++++++++++++++++++++-----
 1 file changed, 37 insertions(+), 6 deletions(-)

diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c
index d9d29d22f..87c9aedf2 100644
--- a/drivers/net/e1000/igb_ethdev.c
+++ b/drivers/net/e1000/igb_ethdev.c
@@ -69,4 +69,7 @@
 #define E1000_VET_VET_EXT_SHIFT      16
 
+/* MSI-X other interrupt vector */
+#define IGB_MSIX_OTHER_INTR_VEC      0
+
 static int  eth_igb_configure(struct rte_eth_dev *dev);
 static int  eth_igb_start(struct rte_eth_dev *dev);
@@ -139,5 +142,5 @@ static int eth_igb_led_on(struct rte_eth_dev *dev);
 static int eth_igb_led_off(struct rte_eth_dev *dev);
 
-static void igb_intr_disable(struct e1000_hw *hw);
+static void igb_intr_disable(struct rte_eth_dev *dev);
 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 static int eth_igb_rar_set(struct rte_eth_dev *dev,
@@ -539,4 +542,11 @@ igb_intr_enable(struct rte_eth_dev *dev)
 	struct e1000_hw *hw =
 		E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
+	struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+
+	if (rte_intr_allow_others(intr_handle) &&
+		dev->data->dev_conf.intr_conf.lsc != 0) {
+		E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
+	}
 
 	E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
@@ -545,6 +555,16 @@ igb_intr_enable(struct rte_eth_dev *dev)
 
 static void
-igb_intr_disable(struct e1000_hw *hw)
+igb_intr_disable(struct rte_eth_dev *dev)
 {
+	struct e1000_hw *hw =
+		E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
+	struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+
+	if (rte_intr_allow_others(intr_handle) &&
+		dev->data->dev_conf.intr_conf.lsc != 0) {
+		E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
+	}
+
 	E1000_WRITE_REG(hw, E1000_IMC, ~0);
 	E1000_WRITE_FLUSH(hw);
@@ -1487,5 +1507,5 @@ eth_igb_stop(struct rte_eth_dev *dev)
 	eth_igb_rxtx_control(dev, false);
 
-	igb_intr_disable(hw);
+	igb_intr_disable(dev);
 
 	/* disable intr eventfd mapping */
@@ -2769,4 +2789,7 @@ static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
 	struct e1000_hw *hw =
 		E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
+	struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+	int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
 	struct rte_eth_dev_info dev_info;
 
@@ -2774,5 +2797,5 @@ static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
 	eth_igb_infos_get(dev, &dev_info);
 
-	mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
+	mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
 	regval = E1000_READ_REG(hw, E1000_EIMS);
 	E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
@@ -2801,5 +2824,5 @@ eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
 		E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 
-	igb_intr_disable(hw);
+	igb_intr_disable(dev);
 
 	/* read-on-clear nic registers here */
@@ -5584,4 +5607,8 @@ eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
 		intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
 			misc_shift;
+
+		if (dev->data->dev_conf.intr_conf.lsc != 0)
+			intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
+
 		regval = E1000_READ_REG(hw, E1000_EIAC);
 		E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
@@ -5590,5 +5617,5 @@ eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
 		regval = E1000_READ_REG(hw, E1000_EIMS);
 		E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
-		tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
+		tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
 		E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
 	}
@@ -5599,4 +5626,8 @@ eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
 	intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
 		misc_shift;
+
+	if (dev->data->dev_conf.intr_conf.lsc != 0)
+		intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
+
 	regval = E1000_READ_REG(hw, E1000_EIAM);
 	E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
-- 
2.19.0

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2018-12-14 18:23:18.261171574 +0000
+++ 0002-net-igb-fix-LSC-interrupt-when-using-MSI-X.patch	2018-12-14 18:23:18.000000000 +0000
@@ -1,8 +1,10 @@
-From 7f5c81d5689d4d1b4dce8279a6eb3318bddf1607 Mon Sep 17 00:00:00 2001
+From c7dd7044fcf39e9bb4665fcc06d388422eaed4ef Mon Sep 17 00:00:00 2001
 From: "Timmons C. Player" <timmons.player at spirent.com>
 Date: Mon, 19 Nov 2018 14:48:54 +0000
 Subject: [PATCH] net/igb: fix LSC interrupt when using MSI-X
 
+[ upstream commit 7f5c81d5689d4d1b4dce8279a6eb3318bddf1607 ]
+
 Take the 'other interrupt' into account when setting up
 MSI-X interrupts and use the proper mask when enabling it.
 Also, rearm the MSI-X vector after the LSC interrupt fires.
@@ -10,8 +12,6 @@
 This change allows both LSC and RXQ interrupts to work at
 the same time when using MSI-X interrupts.
 
-Cc: stable at dpdk.org
-
 Signed-off-by: Timmons C. Player <timmons.player at spirent.com>
 Acked-by: Wei Zhao <wei.zhao1 at intel.com>
 ---