[dpdk-stable] patch 'net/ixgbe/base: fix host interface shadow RAM read' has been queued to stable release 19.11.4
luca.boccassi at gmail.com
luca.boccassi at gmail.com
Fri Jul 24 13:59:32 CEST 2020
Hi,
FYI, your patch has been queued to stable release 19.11.4
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 07/26/20. So please
shout if anyone has objections.
Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.
Thanks.
Luca Boccassi
---
>From e15dd6bff3f8c0b6ce51cbe7062db5f00c20ff39 Mon Sep 17 00:00:00 2001
From: Guinan Sun <guinanx.sun at intel.com>
Date: Thu, 9 Jul 2020 08:00:28 +0000
Subject: [PATCH] net/ixgbe/base: fix host interface shadow RAM read
[ upstream commit 713fc4dd340e5eadd3bfa9a468446afaa5188624 ]
Host interface Shadow RAM Read (0x31) command response
buffer length should be stored in two bytes, instead of one byte.
This patch fixes it.
Fixes: e6102361b1d4 ("net/ixgbe/base: use 2 bytes for flash read command")
Signed-off-by: Mateusz Kowalski <mateusz.kowalski at intel.com>
Signed-off-by: Guinan Sun <guinanx.sun at intel.com>
Reviewed-by: Wei Zhao <wei.zhao1 at intel.com>
---
drivers/net/ixgbe/base/ixgbe_common.c | 3 ++-
drivers/net/ixgbe/base/ixgbe_type.h | 12 ++++++++++++
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ixgbe/base/ixgbe_common.c b/drivers/net/ixgbe/base/ixgbe_common.c
index 4eb98dc19..5889410f9 100644
--- a/drivers/net/ixgbe/base/ixgbe_common.c
+++ b/drivers/net/ixgbe/base/ixgbe_common.c
@@ -4600,7 +4600,8 @@ s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
* Read Flash command requires reading buffer length from
* two byes instead of one byte
*/
- if (resp->cmd == 0x30) {
+ if (resp->cmd == IXGBE_HOST_INTERFACE_FLASH_READ_CMD ||
+ resp->cmd == IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD) {
for (; bi < dword_len + 2; bi++) {
buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
bi);
diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h
index 15e937010..bc927a34e 100644
--- a/drivers/net/ixgbe/base/ixgbe_type.h
+++ b/drivers/net/ixgbe/base/ixgbe_type.h
@@ -4364,4 +4364,16 @@ struct ixgbe_hw {
#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \
(0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
+/* Code Command (Flash I/F Interface) */
+#define IXGBE_HOST_INTERFACE_FLASH_READ_CMD 0x30
+#define IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD 0x31
+#define IXGBE_HOST_INTERFACE_FLASH_WRITE_CMD 0x32
+#define IXGBE_HOST_INTERFACE_SHADOW_RAM_WRITE_CMD 0x33
+#define IXGBE_HOST_INTERFACE_FLASH_MODULE_UPDATE_CMD 0x34
+#define IXGBE_HOST_INTERFACE_FLASH_BLOCK_EREASE_CMD 0x35
+#define IXGBE_HOST_INTERFACE_SHADOW_RAM_DUMP_CMD 0x36
+#define IXGBE_HOST_INTERFACE_FLASH_INFO_CMD 0x37
+#define IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD 0x38
+#define IXGBE_HOST_INTERFACE_MASK_CMD 0x000000FF
+
#endif /* _IXGBE_TYPE_H_ */
--
2.20.1
---
Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- - 2020-07-24 12:53:53.690520459 +0100
+++ 0134-net-ixgbe-base-fix-host-interface-shadow-RAM-read.patch 2020-07-24 12:53:48.435009217 +0100
@@ -1,14 +1,15 @@
-From 713fc4dd340e5eadd3bfa9a468446afaa5188624 Mon Sep 17 00:00:00 2001
+From e15dd6bff3f8c0b6ce51cbe7062db5f00c20ff39 Mon Sep 17 00:00:00 2001
From: Guinan Sun <guinanx.sun at intel.com>
Date: Thu, 9 Jul 2020 08:00:28 +0000
Subject: [PATCH] net/ixgbe/base: fix host interface shadow RAM read
+[ upstream commit 713fc4dd340e5eadd3bfa9a468446afaa5188624 ]
+
Host interface Shadow RAM Read (0x31) command response
buffer length should be stored in two bytes, instead of one byte.
This patch fixes it.
Fixes: e6102361b1d4 ("net/ixgbe/base: use 2 bytes for flash read command")
-Cc: stable at dpdk.org
Signed-off-by: Mateusz Kowalski <mateusz.kowalski at intel.com>
Signed-off-by: Guinan Sun <guinanx.sun at intel.com>
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