[dpdk-stable] patch 'common/qat: fix GEN3 marketing name' has been queued to stable release 19.11.3

[luca.boccassi at gmail.com]

Hi,

FYI, your patch has been queued to stable release 19.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 05/21/20. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Thanks.

Luca Boccassi

---
>From 152fadd540a9f72046a0411522c95997636d1d55 Mon Sep 17 00:00:00 2001
From: Adam Dybkowski <adamx.dybkowski at intel.com>
Date: Wed, 4 Mar 2020 14:18:35 +0100
Subject: [PATCH] common/qat: fix GEN3 marketing name

[ upstream commit 9cd9d3e702fba4700539c1a2eddac13dd14ecf70 ]

This patch fixes the marketing name of the QAT GEN3 to P5xxx.
Updates this name mentioned in the compression PMD as well as
in the documentation.

Fixes: aa983f03ad2e ("crypto/qat: handle Single Pass Crypto Requests on GEN3")
Fixes: a124830a6f00 ("compress/qat: enable dynamic huffman encoding")
Fixes: 1f5e4053f9b4 ("common/qat: support GEN3 devices")

Signed-off-by: Adam Dybkowski <adamx.dybkowski at intel.com>
Acked-by: Fiona Trahe <fiona.trahe at intel.com>
---
 doc/guides/cryptodevs/qat.rst          | 6 +++---
 doc/guides/rel_notes/release_19_11.rst | 2 +-
 drivers/compress/qat/qat_comp_pmd.c    | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 6197875fe3..5ab80b1c0f 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -23,7 +23,7 @@ poll mode crypto driver support for the following hardware accelerator devices:
 * ``Intel QuickAssist Technology C62x``
 * ``Intel QuickAssist Technology C3xxx``
 * ``Intel QuickAssist Technology D15xx``
-* ``Intel QuickAssist Technology C4xxx``
+* ``Intel QuickAssist Technology P5xxx``
 
 
 Features
@@ -122,7 +122,7 @@ poll mode crypto driver support for the following hardware accelerator devices:
 * ``Intel QuickAssist Technology C62x``
 * ``Intel QuickAssist Technology C3xxx``
 * ``Intel QuickAssist Technology D15xx``
-* ``Intel QuickAssist Technology C4xxx``
+* ``Intel QuickAssist Technology P5xxx``
 
 The QAT ASYM PMD has support for:
 
@@ -323,7 +323,7 @@ to see the full table)
    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
    | Yes | No  | No  | 2   | D15xx    | p             | qat_d15xx     | d15xx      | 6f54   | 1    | 6f55   | 16     |
    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
-   | Yes | No  | No  | 3   | C4xxx    | p             | qat_c4xxx     | c4xxx      | 18a0   | 1    | 18a1   | 128    |
+   | Yes | No  | No  | 3   | P5xxx    | p             | qat_p5xxx     | p5xxx      | 18a0   | 1    | 18a1   | 128    |
    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
 
 The first 3 columns indicate the service:
diff --git a/doc/guides/rel_notes/release_19_11.rst b/doc/guides/rel_notes/release_19_11.rst
index 56f169f7f2..edf103b5f6 100644
--- a/doc/guides/rel_notes/release_19_11.rst
+++ b/doc/guides/rel_notes/release_19_11.rst
@@ -260,7 +260,7 @@ New Features
 * **Enabled Single Pass GCM acceleration on QAT GEN3.**
 
   Added support for Single Pass GCM, available on QAT GEN3 only (Intel
-  QuickAssist Technology C4xxx). It is automatically chosen instead of the
+  QuickAssist Technology P5xxx). It is automatically chosen instead of the
   classic 2-pass mode when running on QAT GEN3, significantly improving
   the performance of AES GCM operations.
 
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 05b7dfe774..eb3e422b27 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -663,7 +663,7 @@ int
 qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
 {
 	if (qat_pci_dev->qat_dev_gen == QAT_GEN3) {
-		QAT_LOG(ERR, "Compression PMD not supported on QAT c4xxx");
+		QAT_LOG(ERR, "Compression PMD not supported on QAT P5xxx");
 		return 0;
 	}
 
-- 
2.20.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2020-05-19 13:56:21.315333455 +0100
+++ 0061-common-qat-fix-GEN3-marketing-name.patch	2020-05-19 13:56:18.291503115 +0100
@@ -1,8 +1,10 @@
-From 9cd9d3e702fba4700539c1a2eddac13dd14ecf70 Mon Sep 17 00:00:00 2001
+From 152fadd540a9f72046a0411522c95997636d1d55 Mon Sep 17 00:00:00 2001
 From: Adam Dybkowski <adamx.dybkowski at intel.com>
 Date: Wed, 4 Mar 2020 14:18:35 +0100
 Subject: [PATCH] common/qat: fix GEN3 marketing name
 
+[ upstream commit 9cd9d3e702fba4700539c1a2eddac13dd14ecf70 ]
+
 This patch fixes the marketing name of the QAT GEN3 to P5xxx.
 Updates this name mentioned in the compression PMD as well as
 in the documentation.
@@ -10,7 +12,6 @@
 Fixes: aa983f03ad2e ("crypto/qat: handle Single Pass Crypto Requests on GEN3")
 Fixes: a124830a6f00 ("compress/qat: enable dynamic huffman encoding")
 Fixes: 1f5e4053f9b4 ("common/qat: support GEN3 devices")
-Cc: stable at dpdk.org
 
 Signed-off-by: Adam Dybkowski <adamx.dybkowski at intel.com>
 Acked-by: Fiona Trahe <fiona.trahe at intel.com>
@@ -21,7 +22,7 @@
  3 files changed, 5 insertions(+), 5 deletions(-)
 
 diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
-index 06985e3193..1e83ed6267 100644
+index 6197875fe3..5ab80b1c0f 100644
 --- a/doc/guides/cryptodevs/qat.rst
 +++ b/doc/guides/cryptodevs/qat.rst
 @@ -23,7 +23,7 @@ poll mode crypto driver support for the following hardware accelerator devices:
@@ -33,7 +34,7 @@
  
  
  Features
-@@ -149,7 +149,7 @@ poll mode crypto driver support for the following hardware accelerator devices:
+@@ -122,7 +122,7 @@ poll mode crypto driver support for the following hardware accelerator devices:
  * ``Intel QuickAssist Technology C62x``
  * ``Intel QuickAssist Technology C3xxx``
  * ``Intel QuickAssist Technology D15xx``
@@ -42,7 +43,7 @@
  
  The QAT ASYM PMD has support for:
  
-@@ -376,7 +376,7 @@ to see the full table)
+@@ -323,7 +323,7 @@ to see the full table)
     +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
     | Yes | No  | No  | 2   | D15xx    | p             | qat_d15xx     | d15xx      | 6f54   | 1    | 6f55   | 16     |
     +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
@@ -52,7 +53,7 @@
  
  The first 3 columns indicate the service:
 diff --git a/doc/guides/rel_notes/release_19_11.rst b/doc/guides/rel_notes/release_19_11.rst
-index eb05149f8f..0261d28431 100644
+index 56f169f7f2..edf103b5f6 100644
 --- a/doc/guides/rel_notes/release_19_11.rst
 +++ b/doc/guides/rel_notes/release_19_11.rst
 @@ -260,7 +260,7 @@ New Features
@@ -65,12 +66,12 @@
    the performance of AES GCM operations.
  
 diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
-index 7d4fdf10c2..9a7ed19d76 100644
+index 05b7dfe774..eb3e422b27 100644
 --- a/drivers/compress/qat/qat_comp_pmd.c
 +++ b/drivers/compress/qat/qat_comp_pmd.c
-@@ -666,7 +666,7 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev,
+@@ -663,7 +663,7 @@ int
+ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
  {
- 	int i = 0;
  	if (qat_pci_dev->qat_dev_gen == QAT_GEN3) {
 -		QAT_LOG(ERR, "Compression PMD not supported on QAT c4xxx");
 +		QAT_LOG(ERR, "Compression PMD not supported on QAT P5xxx");