patch 'net/hns3: fix LRO offload to report' has been queued to stable release 22.11.4
Xueming Li
xuemingl at nvidia.com
Mon Dec 11 11:11:01 CET 2023
Hi,
FYI, your patch has been queued to stable release 22.11.4
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 12/13/23. So please
shout if anyone has objections.
Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.
Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging
This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=36f408b7d8be653b1c529b71f8d7651dbc6f4f68
Thanks.
Xueming Li <xuemingl at nvidia.com>
---
>From 36f408b7d8be653b1c529b71f8d7651dbc6f4f68 Mon Sep 17 00:00:00 2001
From: Huisong Li <lihuisong at huawei.com>
Date: Tue, 31 Oct 2023 20:23:55 +0800
Subject: [PATCH] net/hns3: fix LRO offload to report
Cc: Xueming Li <xuemingl at nvidia.com>
[ upstream commit a4b2c6815abd3e39daca2e2c93334b813e6a0be4 ]
Some network engines, like part of HIP09, may not support LRO
offload, but this offload capability is also reported to user.
So this patch determines whether driver reports this capability
based on the capabilities from firmware.
In addition, some network engines, like HIP08, always support LRO
offload and their firmware don't report this capability. So this
patch has to move getting revision ID codes to earlier stage and set
default capabilities for these network engines based on revision ID.
Fixes: ab2e2e344163 ("net/hns3: get device capability in primary process")
Fixes: f5ed7d99cf45 ("net/hns3: extract common function to obtain revision ID")
Signed-off-by: Huisong Li <lihuisong at huawei.com>
Signed-off-by: Jie Hai <haijie1 at huawei.com>
---
drivers/net/hns3/hns3_cmd.c | 17 ++++++++++++++++-
drivers/net/hns3/hns3_cmd.h | 1 +
drivers/net/hns3/hns3_common.c | 5 +++--
drivers/net/hns3/hns3_dump.c | 1 +
drivers/net/hns3/hns3_ethdev.c | 8 ++++----
drivers/net/hns3/hns3_ethdev.h | 1 +
drivers/net/hns3/hns3_ethdev_vf.c | 8 ++++----
drivers/net/hns3/hns3_rxtx.c | 3 +++
8 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c
index 8f5c373acf..1dd4b7a8fc 100644
--- a/drivers/net/hns3/hns3_cmd.c
+++ b/drivers/net/hns3/hns3_cmd.c
@@ -507,6 +507,8 @@ hns3_parse_capability(struct hns3_hw *hw,
hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RAS_IMP_B, 1);
if (hns3_get_bit(caps, HNS3_CAPS_TM_B))
hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TM_B, 1);
+ if (hns3_get_bit(caps, HNS3_CAPS_GRO_B))
+ hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_GRO_B, 1);
}
static uint32_t
@@ -541,6 +543,19 @@ hns3_set_dcb_capability(struct hns3_hw *hw)
hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
}
+static void
+hns3_set_default_capability(struct hns3_hw *hw)
+{
+ hns3_set_dcb_capability(hw);
+
+ /*
+ * The firmware of the network engines with HIP08 do not report some
+ * capabilities, like GRO. Set default capabilities for it.
+ */
+ if (hw->revision < PCI_REVISION_ID_HIP09_A)
+ hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_GRO_B, 1);
+}
+
static int
hns3_cmd_query_firmware_version_and_capability(struct hns3_hw *hw)
{
@@ -559,7 +574,7 @@ hns3_cmd_query_firmware_version_and_capability(struct hns3_hw *hw)
hw->fw_version = rte_le_to_cpu_32(resp->firmware);
- hns3_set_dcb_capability(hw);
+ hns3_set_default_capability(hw);
/*
* Make sure mask the capability before parse capability because it
diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h
index eb394c9dec..0a4d59bd9b 100644
--- a/drivers/net/hns3/hns3_cmd.h
+++ b/drivers/net/hns3/hns3_cmd.h
@@ -322,6 +322,7 @@ enum HNS3_CAPS_BITS {
HNS3_CAPS_RAS_IMP_B,
HNS3_CAPS_RXD_ADV_LAYOUT_B = 15,
HNS3_CAPS_TM_B = 19,
+ HNS3_CAPS_GRO_B = 20,
};
/* Capabilities of VF dependent on the PF */
diff --git a/drivers/net/hns3/hns3_common.c b/drivers/net/hns3/hns3_common.c
index 3dce7a9a31..5d9df03733 100644
--- a/drivers/net/hns3/hns3_common.c
+++ b/drivers/net/hns3/hns3_common.c
@@ -70,8 +70,7 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
RTE_ETH_RX_OFFLOAD_SCATTER |
RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
- RTE_ETH_RX_OFFLOAD_RSS_HASH |
- RTE_ETH_RX_OFFLOAD_TCP_LRO);
+ RTE_ETH_RX_OFFLOAD_RSS_HASH);
info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
@@ -99,6 +98,8 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
if (hns3_dev_get_support(hw, PTP))
info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP;
+ if (hns3_dev_get_support(hw, GRO))
+ info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TCP_LRO;
info->rx_desc_lim = (struct rte_eth_desc_lim) {
.nb_max = HNS3_MAX_RING_DESC,
diff --git a/drivers/net/hns3/hns3_dump.c b/drivers/net/hns3/hns3_dump.c
index e3dbc5ea27..bac4427227 100644
--- a/drivers/net/hns3/hns3_dump.c
+++ b/drivers/net/hns3/hns3_dump.c
@@ -101,6 +101,7 @@ hns3_get_dev_feature_capability(FILE *file, struct hns3_hw *hw)
{HNS3_DEV_SUPPORT_RAS_IMP_B, "RAS IMP"},
{HNS3_DEV_SUPPORT_TM_B, "TM"},
{HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, "VF VLAN FILTER MOD"},
+ {HNS3_DEV_SUPPORT_GRO_B, "GRO"}
};
uint32_t i;
diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c
index 03ddc14eae..f1131f4ba8 100644
--- a/drivers/net/hns3/hns3_ethdev.c
+++ b/drivers/net/hns3/hns3_ethdev.c
@@ -2726,10 +2726,6 @@ hns3_get_capability(struct hns3_hw *hw)
struct hns3_pf *pf = &hns->pf;
int ret;
- ret = hns3_get_pci_revision_id(hw, &hw->revision);
- if (ret)
- return ret;
-
ret = hns3_query_mac_stats_reg_num(hw);
if (ret)
return ret;
@@ -4592,6 +4588,10 @@ hns3_init_pf(struct rte_eth_dev *eth_dev)
/* Get hardware io base address from pcie BAR2 IO space */
hw->io_base = pci_dev->mem_resource[2].addr;
+ ret = hns3_get_pci_revision_id(hw, &hw->revision);
+ if (ret)
+ return ret;
+
/* Firmware command queue initialize */
ret = hns3_cmd_init_queue(hw);
if (ret) {
diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h
index f86512bd35..a3dd4b45c2 100644
--- a/drivers/net/hns3/hns3_ethdev.h
+++ b/drivers/net/hns3/hns3_ethdev.h
@@ -884,6 +884,7 @@ enum hns3_dev_cap {
HNS3_DEV_SUPPORT_RAS_IMP_B,
HNS3_DEV_SUPPORT_TM_B,
HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B,
+ HNS3_DEV_SUPPORT_GRO_B,
};
#define hns3_dev_get_support(hw, _name) \
diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c
index 3874148815..3cbf2ed2a7 100644
--- a/drivers/net/hns3/hns3_ethdev_vf.c
+++ b/drivers/net/hns3/hns3_ethdev_vf.c
@@ -762,10 +762,6 @@ hns3vf_get_capability(struct hns3_hw *hw)
{
int ret;
- ret = hns3_get_pci_revision_id(hw, &hw->revision);
- if (ret)
- return ret;
-
if (hw->revision < PCI_REVISION_ID_HIP09_A) {
hns3_set_default_dev_specifications(hw);
hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
@@ -1418,6 +1414,10 @@ hns3vf_init_vf(struct rte_eth_dev *eth_dev)
/* Get hardware io base address from pcie BAR2 IO space */
hw->io_base = pci_dev->mem_resource[2].addr;
+ ret = hns3_get_pci_revision_id(hw, &hw->revision);
+ if (ret)
+ return ret;
+
/* Firmware command queue initialize */
ret = hns3_cmd_init_queue(hw);
if (ret) {
diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c
index 5db0d3418c..9d473dbc22 100644
--- a/drivers/net/hns3/hns3_rxtx.c
+++ b/drivers/net/hns3/hns3_rxtx.c
@@ -3124,6 +3124,9 @@ hns3_config_gro(struct hns3_hw *hw, bool en)
struct hns3_cmd_desc desc;
int ret;
+ if (!hns3_dev_get_support(hw, GRO))
+ return 0;
+
hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
req = (struct hns3_cfg_gro_status_cmd *)desc.data;
--
2.25.1
---
Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- - 2023-12-11 17:56:24.330617800 +0800
+++ 0036-net-hns3-fix-LRO-offload-to-report.patch 2023-12-11 17:56:22.967652300 +0800
@@ -1 +1 @@
-From a4b2c6815abd3e39daca2e2c93334b813e6a0be4 Mon Sep 17 00:00:00 2001
+From 36f408b7d8be653b1c529b71f8d7651dbc6f4f68 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit a4b2c6815abd3e39daca2e2c93334b813e6a0be4 ]
@@ -18 +20,0 @@
-Cc: stable at dpdk.org
@@ -26 +28 @@
- drivers/net/hns3/hns3_dump.c | 3 ++-
+ drivers/net/hns3/hns3_dump.c | 1 +
@@ -31 +33 @@
- 8 files changed, 34 insertions(+), 12 deletions(-)
+ 8 files changed, 33 insertions(+), 11 deletions(-)
@@ -34 +36 @@
-index 62c55f347f..a5c4c11dc8 100644
+index 8f5c373acf..1dd4b7a8fc 100644
@@ -37 +39,3 @@
-@@ -513,6 +513,8 @@ hns3_parse_capability(struct hns3_hw *hw,
+@@ -507,6 +507,8 @@ hns3_parse_capability(struct hns3_hw *hw,
+ hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RAS_IMP_B, 1);
+ if (hns3_get_bit(caps, HNS3_CAPS_TM_B))
@@ -39,2 +42,0 @@
- if (hns3_get_bit(caps, HNS3_CAPS_FC_AUTO_B))
- hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_FC_AUTO_B, 1);
@@ -46 +48 @@
-@@ -547,6 +549,19 @@ hns3_set_dcb_capability(struct hns3_hw *hw)
+@@ -541,6 +543,19 @@ hns3_set_dcb_capability(struct hns3_hw *hw)
@@ -66 +68 @@
-@@ -565,7 +580,7 @@ hns3_cmd_query_firmware_version_and_capability(struct hns3_hw *hw)
+@@ -559,7 +574,7 @@ hns3_cmd_query_firmware_version_and_capability(struct hns3_hw *hw)
@@ -76 +78 @@
-index 3f2bb4fd29..79a8c1edad 100644
+index eb394c9dec..0a4d59bd9b 100644
@@ -79 +81 @@
-@@ -323,6 +323,7 @@ enum HNS3_CAPS_BITS {
+@@ -322,6 +322,7 @@ enum HNS3_CAPS_BITS {
@@ -84 +85,0 @@
- HNS3_CAPS_FC_AUTO_B = 30,
@@ -86,0 +88 @@
+ /* Capabilities of VF dependent on the PF */
@@ -88 +90 @@
-index c4d47f43fe..9327adbdc1 100644
+index 3dce7a9a31..5d9df03733 100644
@@ -111 +113 @@
-index 5c21ff0a33..cb369be5be 100644
+index e3dbc5ea27..bac4427227 100644
@@ -114 +116 @@
-@@ -104,7 +104,8 @@ hns3_get_dev_feature_capability(FILE *file, struct hns3_hw *hw)
+@@ -101,6 +101,7 @@ hns3_get_dev_feature_capability(FILE *file, struct hns3_hw *hw)
@@ -118,2 +119,0 @@
-- {HNS3_DEV_SUPPORT_FC_AUTO_B, "FC AUTO"}
-+ {HNS3_DEV_SUPPORT_FC_AUTO_B, "FC AUTO"},
@@ -125 +125 @@
-index 472737e8a8..941d047bf1 100644
+index 03ddc14eae..f1131f4ba8 100644
@@ -128 +128 @@
-@@ -2722,10 +2722,6 @@ hns3_get_capability(struct hns3_hw *hw)
+@@ -2726,10 +2726,6 @@ hns3_get_capability(struct hns3_hw *hw)
@@ -139 +139 @@
-@@ -4582,6 +4578,10 @@ hns3_init_pf(struct rte_eth_dev *eth_dev)
+@@ -4592,6 +4588,10 @@ hns3_init_pf(struct rte_eth_dev *eth_dev)
@@ -151 +151 @@
-index 0e8d043704..668f141e32 100644
+index f86512bd35..a3dd4b45c2 100644
@@ -154 +154,2 @@
-@@ -888,6 +888,7 @@ enum hns3_dev_cap {
+@@ -884,6 +884,7 @@ enum hns3_dev_cap {
+ HNS3_DEV_SUPPORT_RAS_IMP_B,
@@ -157 +157,0 @@
- HNS3_DEV_SUPPORT_FC_AUTO_B,
@@ -163 +163 @@
-index 5f3422d14e..0a227e6e45 100644
+index 3874148815..3cbf2ed2a7 100644
@@ -166 +166 @@
-@@ -681,10 +681,6 @@ hns3vf_get_capability(struct hns3_hw *hw)
+@@ -762,10 +762,6 @@ hns3vf_get_capability(struct hns3_hw *hw)
@@ -177 +177 @@
-@@ -1337,6 +1333,10 @@ hns3vf_init_vf(struct rte_eth_dev *eth_dev)
+@@ -1418,6 +1414,10 @@ hns3vf_init_vf(struct rte_eth_dev *eth_dev)
@@ -189 +189 @@
-index f28ca040be..09b7e90c70 100644
+index 5db0d3418c..9d473dbc22 100644
@@ -192 +192 @@
-@@ -3125,6 +3125,9 @@ hns3_config_gro(struct hns3_hw *hw, bool en)
+@@ -3124,6 +3124,9 @@ hns3_config_gro(struct hns3_hw *hw, bool en)
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