patch 'bus/pci: add PASID control' has been queued to stable release 22.11.4

Xueming Li xuemingl at nvidia.com
Mon Dec 11 11:11:30 CET 2023

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Hi,

FYI, your patch has been queued to stable release 22.11.4

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 12/13/23. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=5586a7be436c18b55d006ad4c21cca5ef403eb91

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From 5586a7be436c18b55d006ad4c21cca5ef403eb91 Mon Sep 17 00:00:00 2001
From: Abdullah Sevincer <abdullah.sevincer at intel.com>
Date: Mon, 6 Nov 2023 11:05:20 -0600
Subject: [PATCH] bus/pci: add PASID control
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit 60ea19609aecbd644d7ad7cb86ae06dd76291cf9 ]

Add an internal API to control PASID for a given PCIe device.

For kernels when PASID enabled by default it breaks DLB functionality,
hence disabling PASID is required for DLB to function properly.

PASID capability is not exposed to users hence offset can not be
retrieved by rte_pci_find_ext_capability() API.
Therefore, API implemented in this commit accepts an offset
for PASID with an enable flag which is used to enable/disable PASID.

Signed-off-by: Abdullah Sevincer <abdullah.sevincer at intel.com>
---
 drivers/bus/pci/pci_common.c  | 10 ++++++++++
 drivers/bus/pci/rte_bus_pci.h | 14 ++++++++++++++
 drivers/bus/pci/version.map   |  1 +
 lib/pci/rte_pci.h             |  4 ++++
 4 files changed, 29 insertions(+)

diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c
index e83d77090b..756e308fdf 100644
--- a/drivers/bus/pci/pci_common.c
+++ b/drivers/bus/pci/pci_common.c
@@ -884,6 +884,16 @@ rte_pci_set_bus_master(struct rte_pci_device *dev, bool enable)
 	return 0;
 }
 
+int
+rte_pci_pasid_set_state(const struct rte_pci_device *dev,
+		off_t offset, bool enable)
+{
+	uint16_t pasid = enable;
+	return rte_pci_write_config(dev, &pasid, sizeof(pasid), offset) < 0
+		? -1
+		: 0;
+}
+
 struct rte_pci_bus rte_pci_bus = {
 	.bus = {
 		.scan = rte_pci_scan,
diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h
index b193114fe5..76cbf49ab8 100644
--- a/drivers/bus/pci/rte_bus_pci.h
+++ b/drivers/bus/pci/rte_bus_pci.h
@@ -101,6 +101,20 @@ off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap);
 __rte_experimental
 int rte_pci_set_bus_master(struct rte_pci_device *dev, bool enable);
 
+/**
+ * Enable/Disable PASID (Process Address Space ID).
+ *
+ * @param dev
+ *   A pointer to a rte_pci_device structure.
+ * @param offset
+ *   Offset of the PASID external capability.
+ * @param enable
+ *   Flag to enable or disable PASID.
+ */
+__rte_internal
+int rte_pci_pasid_set_state(const struct rte_pci_device *dev,
+		off_t offset, bool enable);
+
 /**
  * Read PCI config space.
  *
diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map
index 161ab86d3b..f262af3316 100644
--- a/drivers/bus/pci/version.map
+++ b/drivers/bus/pci/version.map
@@ -27,6 +27,7 @@ INTERNAL {
 	global:
 
 	rte_pci_get_sysfs_path;
+	rte_pci_pasid_set_state;
 	rte_pci_register;
 	rte_pci_unregister;
 };
diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
index aab761b918..9876c3fb9d 100644
--- a/lib/pci/rte_pci.h
+++ b/lib/pci/rte_pci.h
@@ -45,6 +45,7 @@ extern "C" {
 #define RTE_PCI_EXT_CAP_ID_ERR		0x01	/* Advanced Error Reporting */
 #define RTE_PCI_EXT_CAP_ID_DSN		0x03	/* Device Serial Number */
 #define RTE_PCI_EXT_CAP_ID_SRIOV	0x10	/* SR-IOV*/
+#define RTE_PCI_EXT_CAP_ID_PASID	0x1B    /* Process Address Space ID */
 
 /* Single Root I/O Virtualization */
 #define RTE_PCI_SRIOV_CAP		0x04	/* SR-IOV Capabilities */
@@ -58,6 +59,9 @@ extern "C" {
 #define RTE_PCI_SRIOV_VF_DID		0x1a	/* VF Device ID */
 #define RTE_PCI_SRIOV_SUP_PGSIZE	0x1c	/* Supported Page Sizes */
 
+
+/* Process Address Space ID (RTE_PCI_EXT_CAP_ID_PASID) */
+#define RTE_PCI_PASID_CTRL		0x06    /* PASID control register */
 /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */
 #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
 #define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X")
-- 
2.25.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2023-12-11 17:56:25.219632200 +0800
+++ 0065-bus-pci-add-PASID-control.patch	2023-12-11 17:56:23.067652300 +0800
@@ -1 +1 @@
-From 60ea19609aecbd644d7ad7cb86ae06dd76291cf9 Mon Sep 17 00:00:00 2001
+From 5586a7be436c18b55d006ad4c21cca5ef403eb91 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit 60ea19609aecbd644d7ad7cb86ae06dd76291cf9 ]
@@ -16,2 +18,0 @@
-Cc: stable at dpdk.org
-
@@ -27 +28 @@
-index 921d957bf6..ba5e280d33 100644
+index e83d77090b..756e308fdf 100644
@@ -30 +31 @@
-@@ -938,6 +938,16 @@ rte_pci_set_bus_master(const struct rte_pci_device *dev, bool enable)
+@@ -884,6 +884,16 @@ rte_pci_set_bus_master(struct rte_pci_device *dev, bool enable)
@@ -48 +49 @@
-index 21e234abf0..f07bf9b588 100644
+index b193114fe5..76cbf49ab8 100644
@@ -51 +52 @@
-@@ -155,6 +155,20 @@ off_t rte_pci_find_ext_capability(const struct rte_pci_device *dev, uint32_t cap
+@@ -101,6 +101,20 @@ off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap);
@@ -53 +54 @@
- int rte_pci_set_bus_master(const struct rte_pci_device *dev, bool enable);
+ int rte_pci_set_bus_master(struct rte_pci_device *dev, bool enable);
@@ -73 +74 @@
-index 74c5b075d5..9e4d8f5e54 100644
+index 161ab86d3b..f262af3316 100644
@@ -76 +77 @@
-@@ -36,6 +36,7 @@ INTERNAL {
+@@ -27,6 +27,7 @@ INTERNAL {
@@ -85 +86 @@
-index 69e932d910..0d2d8d8fed 100644
+index aab761b918..9876c3fb9d 100644
@@ -88,4 +89,4 @@
-@@ -101,6 +101,7 @@ extern "C" {
- #define RTE_PCI_EXT_CAP_ID_ACS		0x0d	/* Access Control Services */
- #define RTE_PCI_EXT_CAP_ID_SRIOV	0x10	/* SR-IOV */
- #define RTE_PCI_EXT_CAP_ID_PRI		0x13	/* Page Request Interface */
+@@ -45,6 +45,7 @@ extern "C" {
+ #define RTE_PCI_EXT_CAP_ID_ERR		0x01	/* Advanced Error Reporting */
+ #define RTE_PCI_EXT_CAP_ID_DSN		0x03	/* Device Serial Number */
+ #define RTE_PCI_EXT_CAP_ID_SRIOV	0x10	/* SR-IOV*/
@@ -94,5 +95,5 @@
- /* Advanced Error Reporting (RTE_PCI_EXT_CAP_ID_ERR) */
- #define RTE_PCI_ERR_UNCOR_STATUS	0x04	/* Uncorrectable Error Status */
-@@ -133,6 +134,9 @@ extern "C" {
- #define RTE_PCI_PRI_CTRL_ENABLE		0x0001	/* Enable */
- #define RTE_PCI_PRI_ALLOC_REQ		0x0c	/* PRI max reqs allowed */
+ /* Single Root I/O Virtualization */
+ #define RTE_PCI_SRIOV_CAP		0x04	/* SR-IOV Capabilities */
+@@ -58,6 +59,9 @@ extern "C" {
+ #define RTE_PCI_SRIOV_VF_DID		0x1a	/* VF Device ID */
+ #define RTE_PCI_SRIOV_SUP_PGSIZE	0x1c	/* Supported Page Sizes */
@@ -99,0 +101 @@
++
@@ -102 +103,0 @@
-+

Previous message (by thread): patch 'build: add libarchive to optional external dependencies' has been queued to stable release 22.11.4
Next message (by thread): patch 'event/dlb2: disable PASID' has been queued to stable release 22.11.4
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