patch 'common/cnxk: reduce channel count per LMAC' has been queued to stable release 22.11.2

[Xueming Li]

Hi,

FYI, your patch has been queued to stable release 22.11.2

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 03/01/23. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=d7d670cbe2370d5e71a694669597ffa11071949e

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From d7d670cbe2370d5e71a694669597ffa11071949e Mon Sep 17 00:00:00 2001
From: Sunil Kumar Kori <skori at marvell.com>
Date: Wed, 4 Jan 2023 11:37:12 +0530
Subject: [PATCH] common/cnxk: reduce channel count per LMAC
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit 869f5bc370d70874b8a49b34aff39709a2b6f8fe ]

Due to limitation, imposed by latest AF kernel driver, maximum number of
channel supported per LMAC is reduced to 8. Because of this change
application gets failed to initialize for more channels.

Also this limitation impacts PFC functional behaviour.

So patch just aligns the supported number of channel with AF kernel
driver.

Fixes: 20d02329cdc2 ("common/cnxk: support priority flow control")

Signed-off-by: Sunil Kumar Kori <skori at marvell.com>
---
 drivers/common/cnxk/roc_mbox.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 8b0384c737..fd9d3e73cd 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -1169,7 +1169,7 @@ struct nix_bp_cfg_req {
  * so maximum 256 channels are possible.
  */
 #define NIX_MAX_CHAN	 256
-#define NIX_CGX_MAX_CHAN 16
+#define NIX_CGX_MAX_CHAN 8
 #define NIX_LBK_MAX_CHAN 1
 struct nix_bp_cfg_rsp {
 	struct mbox_msghdr hdr;
--
2.25.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2023-02-27 14:08:43.288445800 +0800
+++ 0075-common-cnxk-reduce-channel-count-per-LMAC.patch	2023-02-27 14:08:40.799237000 +0800
@@ -1 +1 @@
-From 869f5bc370d70874b8a49b34aff39709a2b6f8fe Mon Sep 17 00:00:00 2001
+From d7d670cbe2370d5e71a694669597ffa11071949e Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit 869f5bc370d70874b8a49b34aff39709a2b6f8fe ]
@@ -16 +18,0 @@
-Cc: stable at dpdk.org
@@ -24 +26 @@
-index 0989bddc3b..b74eb71275 100644
+index 8b0384c737..fd9d3e73cd 100644
@@ -27 +29 @@
-@@ -1173,7 +1173,7 @@ struct nix_bp_cfg_req {
+@@ -1169,7 +1169,7 @@ struct nix_bp_cfg_req {