patch 'net/ice/base: fix GCS descriptor field offsets' has been queued to stable release 23.11.2

[Xueming Li]

Hi,

FYI, your patch has been queued to stable release 23.11.2

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 08/14/24. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=c9eae16d5efb1a8724417604c8e492110a264133

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From c9eae16d5efb1a8724417604c8e492110a264133 Mon Sep 17 00:00:00 2001
From: Eric Joyner <eric.joyner at intel.com>
Date: Wed, 26 Jun 2024 12:41:09 +0100
Subject: [PATCH] net/ice/base: fix GCS descriptor field offsets
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit 243ec291b1eba3ddf7554c9c80a173e9aee58b68 ]

Update the offsets, and remove the ICE_TX_GCS_DESC_ENA define since a
non-0 value used for the ICE_TX_GCS_DESC_TYPE field will enable GCS
offload; there is no dedicated bit to enable it anymore.

Fixes: c31095a0b20f ("net/ice/base: add GCO defines and GCO flex descriptor")

Signed-off-by: Eric Joyner <eric.joyner at intel.com>
Signed-off-by: Ian Stokes <ian.stokes at intel.com>
Acked-by: Bruce Richardson <bruce.richardson at intel.com>
---
 drivers/net/ice/base/ice_lan_tx_rx.h | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index d816df0ff6..39673e36f7 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -1074,10 +1074,9 @@ struct ice_tx_ctx_desc {
 	__le64 qw1;
 };
 
-#define ICE_TX_GSC_DESC_START	0  /* 7 BITS */
-#define ICE_TX_GSC_DESC_OFFSET	7  /* 4 BITS */
-#define ICE_TX_GSC_DESC_TYPE	11 /* 2 BITS */
-#define ICE_TX_GSC_DESC_ENA	13 /* 1 BIT */
+#define ICE_TX_GCS_DESC_START	0  /* 8 BITS */
+#define ICE_TX_GCS_DESC_OFFSET	8  /* 4 BITS */
+#define ICE_TX_GCS_DESC_TYPE	12 /* 3 BITS */
 
 #define ICE_TXD_CTX_QW1_DTYPE_S	0
 #define ICE_TXD_CTX_QW1_DTYPE_M	(0xFUL << ICE_TXD_CTX_QW1_DTYPE_S)
-- 
2.34.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2024-08-12 20:44:04.419904348 +0800
+++ 0056-net-ice-base-fix-GCS-descriptor-field-offsets.patch	2024-08-12 20:44:02.095069294 +0800
@@ -1 +1 @@
-From 243ec291b1eba3ddf7554c9c80a173e9aee58b68 Mon Sep 17 00:00:00 2001
+From c9eae16d5efb1a8724417604c8e492110a264133 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit 243ec291b1eba3ddf7554c9c80a173e9aee58b68 ]
@@ -11 +13,0 @@
-Cc: stable at dpdk.org