patch 'net/mlx5: fix real time counter reading from PCI BAR' has been queued to stable release 23.11.3

[Xueming Li]

Hi,

FYI, your patch has been queued to stable release 23.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 12/10/24. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=9af26e2cde2f4fbe57c53faa678e4d92dc5c17c0

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From 9af26e2cde2f4fbe57c53faa678e4d92dc5c17c0 Mon Sep 17 00:00:00 2001
From: Tim Martin <timothym at nvidia.com>
Date: Mon, 14 Oct 2024 11:04:32 +0300
Subject: [PATCH] net/mlx5: fix real time counter reading from PCI BAR
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit 27918f0d53f482fa97f2a8dcd5792c23094abcec ]

There is the mlx5_txpp_read_clock() routine reading
the 64-bit real time counter from the device PCI BAR.
It introduced two issues:

  - it checks the PCI BAR mapping into process address
    space and tries to map this on demand. This might be
    problematic if something goes wrong and mapping fails.
    It happens on every read_clock API call, invokes kernel
    taking a long time and causing application malfunction.

  - the 64-bit counter should be read in single atomic
    transaction

Fixes: 9b31fc9007f9 ("net/mlx5: fix read device clock in real time mode")

Signed-off-by: Tim Martin <timothym at nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo at nvidia.com>
---
 .mailmap                     |  1 +
 drivers/net/mlx5/mlx5.c      |  4 ++++
 drivers/net/mlx5/mlx5_tx.h   | 34 +++++++++++++++++++++++++++++++++-
 drivers/net/mlx5/mlx5_txpp.c | 11 ++---------
 4 files changed, 40 insertions(+), 10 deletions(-)

diff --git a/.mailmap b/.mailmap
index 8a0ce733c3..7990edf2d0 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1456,6 +1456,7 @@ Timmons C. Player <timmons.player at spirent.com>
 Timothy McDaniel <timothy.mcdaniel at intel.com>
 Timothy Miskell <timothy.miskell at intel.com>
 Timothy Redaelli <tredaelli at redhat.com>
+Tim Martin <timothym at nvidia.com>
 Tim Shearer <tim.shearer at overturenetworks.com>
 Ting-Kai Ku <ting-kai.ku at intel.com>
 Ting Xu <ting.xu at intel.com>
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 8d4a0a3dda..25182bce39 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -2164,6 +2164,7 @@ int
 mlx5_proc_priv_init(struct rte_eth_dev *dev)
 {
 	struct mlx5_priv *priv = dev->data->dev_private;
+	struct mlx5_dev_ctx_shared *sh = priv->sh;
 	struct mlx5_proc_priv *ppriv;
 	size_t ppriv_size;

@@ -2184,6 +2185,9 @@ mlx5_proc_priv_init(struct rte_eth_dev *dev)
 	dev->process_private = ppriv;
 	if (rte_eal_process_type() == RTE_PROC_PRIMARY)
 		priv->sh->pppriv = ppriv;
+	/* Check and try to map HCA PCI BAR to allow reading real time. */
+	if (sh->dev_cap.rt_timestamp && mlx5_dev_is_pci(dev->device))
+		mlx5_txpp_map_hca_bar(dev);
 	return 0;
 }

diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h
index e59ce37667..42fc7ba3b3 100644
--- a/drivers/net/mlx5/mlx5_tx.h
+++ b/drivers/net/mlx5/mlx5_tx.h
@@ -369,6 +369,38 @@ mlx5_txpp_convert_tx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t mts)
 	return ci;
 }

+/**
+ * Read real time clock counter directly from the device PCI BAR area.
+ * The PCI BAR must be mapped to the process memory space at initialization.
+ *
+ * @param dev
+ *   Device to read clock counter from
+ *
+ * @return
+ *   0 - if HCA BAR is not supported or not mapped.
+ *   !=0 - read 64-bit value of real-time in UTC formatv (nanoseconds)
+ */
+static __rte_always_inline uint64_t mlx5_read_pcibar_clock(struct rte_eth_dev *dev)
+{
+	struct mlx5_proc_priv *ppriv = dev->process_private;
+
+	if (ppriv && ppriv->hca_bar) {
+		struct mlx5_priv *priv = dev->data->dev_private;
+		struct mlx5_dev_ctx_shared *sh = priv->sh;
+		uint64_t *hca_ptr = (uint64_t *)(ppriv->hca_bar) +
+				  __mlx5_64_off(initial_seg, real_time);
+		uint64_t __rte_atomic *ts_addr;
+		uint64_t ts;
+
+		ts_addr = (uint64_t __rte_atomic *)hca_ptr;
+		ts = rte_atomic_load_explicit(ts_addr, rte_memory_order_seq_cst);
+		ts = rte_be_to_cpu_64(ts);
+		ts = mlx5_txpp_convert_rx_ts(sh, ts);
+		return ts;
+	}
+	return 0;
+}
+
 /**
  * Set Software Parser flags and offsets in Ethernet Segment of WQE.
  * Flags must be preliminary initialized to zero.
@@ -819,7 +851,7 @@ mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq,
 		cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
 				     MLX5_COMP_MODE_OFFSET);
 	cs->misc = RTE_BE32(0);
-	if (__rte_trace_point_fp_is_enabled() && !loc->pkts_sent)
+	if (__rte_trace_point_fp_is_enabled())
 		rte_pmd_mlx5_trace_tx_entry(txq->port_id, txq->idx);
 	rte_pmd_mlx5_trace_tx_wqe((txq->wqe_ci << 8) | opcode);
 }
diff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c
index 5a5df2d1bb..0184060c3f 100644
--- a/drivers/net/mlx5/mlx5_txpp.c
+++ b/drivers/net/mlx5/mlx5_txpp.c
@@ -971,7 +971,6 @@ mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp)
 {
 	struct mlx5_priv *priv = dev->data->dev_private;
 	struct mlx5_dev_ctx_shared *sh = priv->sh;
-	struct mlx5_proc_priv *ppriv;
 	uint64_t ts;
 	int ret;

@@ -997,15 +996,9 @@ mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp)
 		*timestamp = ts;
 		return 0;
 	}
-	/* Check and try to map HCA PIC BAR to allow reading real time. */
-	ppriv = dev->process_private;
-	if (ppriv && !ppriv->hca_bar &&
-	    sh->dev_cap.rt_timestamp && mlx5_dev_is_pci(dev->device))
-		mlx5_txpp_map_hca_bar(dev);
 	/* Check if we can read timestamp directly from hardware. */
-	if (ppriv && ppriv->hca_bar) {
-		ts = MLX5_GET64(initial_seg, ppriv->hca_bar, real_time);
-		ts = mlx5_txpp_convert_rx_ts(sh, ts);
+	ts = mlx5_read_pcibar_clock(dev);
+	if (ts != 0) {
 		*timestamp = ts;
 		return 0;
 	}
--
2.34.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2024-12-06 23:26:44.479596122 +0800
+++ 0010-net-mlx5-fix-real-time-counter-reading-from-PCI-BAR.patch	2024-12-06 23:26:43.853044829 +0800
@@ -1 +1 @@
-From 27918f0d53f482fa97f2a8dcd5792c23094abcec Mon Sep 17 00:00:00 2001
+From 9af26e2cde2f4fbe57c53faa678e4d92dc5c17c0 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit 27918f0d53f482fa97f2a8dcd5792c23094abcec ]
@@ -20 +22,0 @@
-Cc: stable at dpdk.org
@@ -32 +34 @@
-index 5290420258..504c390f0f 100644
+index 8a0ce733c3..7990edf2d0 100644
@@ -35 +37 @@
-@@ -1523,6 +1523,7 @@ Timmons C. Player <timmons.player at spirent.com>
+@@ -1456,6 +1456,7 @@ Timmons C. Player <timmons.player at spirent.com>
@@ -44 +46 @@
-index e36fa651a1..52b90e6ff3 100644
+index 8d4a0a3dda..25182bce39 100644
@@ -47 +49 @@
-@@ -2242,6 +2242,7 @@ int
+@@ -2164,6 +2164,7 @@ int
@@ -55 +57 @@
-@@ -2262,6 +2263,9 @@ mlx5_proc_priv_init(struct rte_eth_dev *dev)
+@@ -2184,6 +2185,9 @@ mlx5_proc_priv_init(struct rte_eth_dev *dev)
@@ -66 +68 @@
-index 983913faa2..587e6a9f7d 100644
+index e59ce37667..42fc7ba3b3 100644
@@ -69 +71 @@
-@@ -372,6 +372,38 @@ mlx5_txpp_convert_tx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t mts)
+@@ -369,6 +369,38 @@ mlx5_txpp_convert_tx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t mts)
@@ -108 +110 @@
-@@ -822,7 +854,7 @@ mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq,
+@@ -819,7 +851,7 @@ mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq,
@@ -118 +120 @@
-index 4e26fa2db8..e6d3ad83e9 100644
+index 5a5df2d1bb..0184060c3f 100644