patch 'net/axgbe: fix Tx flow on 30H HW' has been queued to stable release 22.11.6

luca.boccassi at gmail.com luca.boccassi at gmail.com
Tue Jun 25 01:58:18 CEST 2024


Hi,

FYI, your patch has been queued to stable release 22.11.6

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 06/27/24. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/bluca/dpdk-stable

This queued commit can be viewed at:
https://github.com/bluca/dpdk-stable/commit/59767090cb7af04ec5fbdc8a443cd3da13f0207c

Thanks.

Luca Boccassi

---
>From 59767090cb7af04ec5fbdc8a443cd3da13f0207c Mon Sep 17 00:00:00 2001
From: Venkat Kumar Ande <venkatkumar.ande at amd.com>
Date: Tue, 4 Jun 2024 17:41:43 +0530
Subject: [PATCH] net/axgbe: fix Tx flow on 30H HW

[ upstream commit b4b24f3e80f9b1bd2c56e1b56b8b8337748e15e6 ]

There is difference in the TX Flow Control registers (TFCR) between the
revisions of the hardware. The older revisions of hardware used to have
single register per queue. Whereas, the newer revision of hardware (from
ver 30H onwards) have one register per priority.

Without the fix the user will face problem in TX operation on new 30H HW

Fixes: 7c4158a5b592 ("net/axgbe: add DMA programming and start/stop")

Signed-off-by: Venkat Kumar Ande <venkatkumar.ande at amd.com>
Acked-by: Selwin Sebastian <selwin.sebastian at amd.com>
---
 drivers/net/axgbe/axgbe_dev.c | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
index 9b0073eea6..5233633a53 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -269,20 +269,28 @@ static int axgbe_set_speed(struct axgbe_port *pdata, int speed)
 	return 0;
 }
 
+static unsigned int axgbe_get_fc_queue_count(struct axgbe_port *pdata)
+{
+	unsigned int max_q_count = AXGMAC_MAX_FLOW_CONTROL_QUEUES;
+
+	/* From MAC ver 30H the TFCR is per priority, instead of per queue */
+	if (AXGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) >= 0x30)
+		return max_q_count;
+	else
+		return (RTE_MIN(pdata->tx_q_count, max_q_count));
+}
+
 static int axgbe_disable_tx_flow_control(struct axgbe_port *pdata)
 {
-	unsigned int max_q_count, q_count;
 	unsigned int reg, reg_val;
-	unsigned int i;
+	unsigned int i, q_count;
 
 	/* Clear MTL flow control */
 	for (i = 0; i < pdata->rx_q_count; i++)
 		AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
 
 	/* Clear MAC flow control */
-	max_q_count = AXGMAC_MAX_FLOW_CONTROL_QUEUES;
-	q_count = RTE_MIN(pdata->tx_q_count,
-			max_q_count);
+	q_count = axgbe_get_fc_queue_count(pdata);
 	reg = MAC_Q0TFCR;
 	for (i = 0; i < q_count; i++) {
 		reg_val = AXGMAC_IOREAD(pdata, reg);
@@ -297,9 +305,8 @@ static int axgbe_disable_tx_flow_control(struct axgbe_port *pdata)
 
 static int axgbe_enable_tx_flow_control(struct axgbe_port *pdata)
 {
-	unsigned int max_q_count, q_count;
 	unsigned int reg, reg_val;
-	unsigned int i;
+	unsigned int i, q_count;
 
 	/* Set MTL flow control */
 	for (i = 0; i < pdata->rx_q_count; i++) {
@@ -316,9 +323,7 @@ static int axgbe_enable_tx_flow_control(struct axgbe_port *pdata)
 	}
 
 	/* Set MAC flow control */
-	max_q_count = AXGMAC_MAX_FLOW_CONTROL_QUEUES;
-	q_count = RTE_MIN(pdata->tx_q_count,
-			max_q_count);
+	q_count = axgbe_get_fc_queue_count(pdata);
 	reg = MAC_Q0TFCR;
 	for (i = 0; i < q_count; i++) {
 		reg_val = AXGMAC_IOREAD(pdata, reg);
-- 
2.39.2

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2024-06-25 00:22:15.544399094 +0100
+++ 0032-net-axgbe-fix-Tx-flow-on-30H-HW.patch	2024-06-25 00:22:13.125184426 +0100
@@ -1 +1 @@
-From b4b24f3e80f9b1bd2c56e1b56b8b8337748e15e6 Mon Sep 17 00:00:00 2001
+From 59767090cb7af04ec5fbdc8a443cd3da13f0207c Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit b4b24f3e80f9b1bd2c56e1b56b8b8337748e15e6 ]
+
@@ -14 +15,0 @@
-Cc: stable at dpdk.org


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