[PATCH] net/mlx5: fix the GRE mask set on root table

[Gregory Etelson]

From: Bing Zhao <bingz at nvidia.com>

When setting the value, the GRE mask cannot reuse the one from the
value, or else the value cannot be really ANDed with the proper input
mask from the user. If the value contains more valid bits than the
mask, the rule insertion on the root table will get a failure due to
the extra bits in the value field.

Using the input mask or the default mask will help to clear the extra
bits and solve the issue.

Fixes: 25ab2cbba31d ("net/mlx5: fix GRE item translation for root table")

cc: stable at dpdk.org

Signed-off-by: Bing Zhao <bingz at nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_dv.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 41ebe0b61a..c65345e6ac 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -9853,8 +9853,6 @@ flow_dv_translate_item_gre(void *key, const struct rte_flow_item *item,
 		} else if (!gre_m) {
 			gre_m = &rte_flow_item_gre_mask;
 		}
-		if (key_type == MLX5_SET_MATCHER_HS_V)
-			gre_m = gre_v;
 	}
 	gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
 	gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
-- 
2.45.2