patch 'event/cnxk: fix missing HW state checks' has been queued to stable release 24.11.3
Kevin Traynor
ktraynor at redhat.com
Fri Jul 18 21:29:12 CEST 2025
Hi,
FYI, your patch has been queued to stable release 24.11.3
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 07/23/25. So please
shout if anyone has objections.
Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.
Queued patches are on a temporary branch at:
https://github.com/kevintraynor/dpdk-stable
This queued commit can be viewed at:
https://github.com/kevintraynor/dpdk-stable/commit/717b7326e4f851b09773171e9922fa0926b5d0a8
Thanks.
Kevin
---
>From 717b7326e4f851b09773171e9922fa0926b5d0a8 Mon Sep 17 00:00:00 2001
From: Pavan Nikhilesh <pbhagavatula at marvell.com>
Date: Thu, 10 Apr 2025 23:35:44 +0530
Subject: [PATCH] event/cnxk: fix missing HW state checks
[ upstream commit f77eb8f3c655a2573aed77bea122d98efc12edef ]
Fix missing HW state checks in timer arm routine in the cases where
thread has been scheduled out while holding a bucket lock.
Fixes: 300b796262a1 ("event/cnxk: add timer arm routine")
Signed-off-by: Pavan Nikhilesh <pbhagavatula at marvell.com>
---
drivers/event/cnxk/cnxk_tim_worker.h | 140 ++++++++++++++-------------
1 file changed, 73 insertions(+), 67 deletions(-)
diff --git a/drivers/event/cnxk/cnxk_tim_worker.h b/drivers/event/cnxk/cnxk_tim_worker.h
index 6a9ee2fd52..09f84091ab 100644
--- a/drivers/event/cnxk/cnxk_tim_worker.h
+++ b/drivers/event/cnxk/cnxk_tim_worker.h
@@ -103,5 +103,5 @@ static inline void
cnxk_tim_bkt_inc_nent(struct cnxk_tim_bkt *bktp)
{
- rte_atomic_fetch_add_explicit(&bktp->nb_entry, 1, rte_memory_order_relaxed);
+ rte_atomic_fetch_add_explicit(&bktp->nb_entry, 1, rte_memory_order_release);
}
@@ -133,4 +133,31 @@ cnxk_tim_bkt_fast_mod(uint64_t n, uint64_t d, struct rte_reciprocal_u64 R)
}
+static inline uint64_t
+cnxk_tim_bkt_wait_hbt(struct cnxk_tim_bkt *bkt)
+{
+ uint64_t hbt_state;
+
+#ifdef RTE_ARCH_ARM64
+ asm volatile(PLT_CPU_FEATURE_PREAMBLE
+ " ldxr %[hbt], [%[w1]] \n"
+ " tbz %[hbt], 33, .Ldne%= \n"
+ " sevl \n"
+ ".Lrty%=: wfe \n"
+ " ldxr %[hbt], [%[w1]] \n"
+ " tbnz %[hbt], 33, .Lrty%=\n"
+ ".Ldne%=: \n"
+ : [hbt] "=&r"(hbt_state)
+ : [w1] "r"((&bkt->w1))
+ : "memory");
+#else
+ do {
+ hbt_state = rte_atomic_load_explicit(&bkt->w1,
+ rte_memory_order_relaxed);
+ } while (hbt_state & BIT_ULL(33));
+#endif
+
+ return hbt_state;
+}
+
static inline void
cnxk_tim_format_event(const struct rte_event_timer *const tim, struct cnxk_tim_ent *const entry)
@@ -266,23 +293,14 @@ __retry:
if (unlikely(cnxk_tim_bkt_get_hbt(lock_sema))) {
if (cnxk_tim_bkt_get_nent(lock_sema) != 0) {
- uint64_t hbt_state;
-#ifdef RTE_ARCH_ARM64
- asm volatile(PLT_CPU_FEATURE_PREAMBLE
- " ldxr %[hbt], [%[w1]] \n"
- " tbz %[hbt], 33, .Ldne%= \n"
- " sevl \n"
- ".Lrty%=: wfe \n"
- " ldxr %[hbt], [%[w1]] \n"
- " tbnz %[hbt], 33, .Lrty%=\n"
- ".Ldne%=: \n"
- : [hbt] "=&r"(hbt_state)
- : [w1] "r"((&bkt->w1))
- : "memory");
-#else
- do {
- hbt_state = rte_atomic_load_explicit(&bkt->w1,
- rte_memory_order_relaxed);
- } while (hbt_state & BIT_ULL(33));
-#endif
+ uint64_t hbt_state = cnxk_tim_bkt_wait_hbt(bkt);
+
+ if (cnxk_tim_bkt_get_nent(lock_sema) != 0 &&
+ cnxk_tim_bkt_get_nent(hbt_state) == 0) {
+ cnxk_tim_bkt_dec_lock(bkt);
+ goto __retry;
+ }
+
+ if (cnxk_tim_bkt_get_nent(hbt_state) != 0)
+ hbt_state |= BIT_ULL(34);
if (!(hbt_state & BIT_ULL(34)) ||
@@ -291,4 +309,6 @@ __retry:
goto __retry;
}
+ } else {
+ cnxk_tim_bkt_wait_hbt(bkt);
}
}
@@ -322,7 +342,7 @@ __retry:
tim->impl_opaque[0] = (uintptr_t)chunk;
tim->impl_opaque[1] = (uintptr_t)bkt;
- rte_atomic_store_explicit(&tim->state, RTE_EVENT_TIMER_ARMED, rte_memory_order_release);
+ tim->state = RTE_EVENT_TIMER_ARMED;
cnxk_tim_bkt_inc_nent(bkt);
- cnxk_tim_bkt_dec_lock_relaxed(bkt);
+ cnxk_tim_bkt_dec_lock(bkt);
return 0;
@@ -349,23 +369,14 @@ __retry:
if (unlikely(cnxk_tim_bkt_get_hbt(lock_sema))) {
if (cnxk_tim_bkt_get_nent(lock_sema) != 0) {
- uint64_t hbt_state;
-#ifdef RTE_ARCH_ARM64
- asm volatile(PLT_CPU_FEATURE_PREAMBLE
- " ldxr %[hbt], [%[w1]] \n"
- " tbz %[hbt], 33, .Ldne%= \n"
- " sevl \n"
- ".Lrty%=: wfe \n"
- " ldxr %[hbt], [%[w1]] \n"
- " tbnz %[hbt], 33, .Lrty%=\n"
- ".Ldne%=: \n"
- : [hbt] "=&r"(hbt_state)
- : [w1] "r"((&bkt->w1))
- : "memory");
-#else
- do {
- hbt_state = rte_atomic_load_explicit(&bkt->w1,
- rte_memory_order_relaxed);
- } while (hbt_state & BIT_ULL(33));
-#endif
+ uint64_t hbt_state = cnxk_tim_bkt_wait_hbt(bkt);
+
+ if (cnxk_tim_bkt_get_nent(lock_sema) != 0 &&
+ cnxk_tim_bkt_get_nent(hbt_state) == 0) {
+ cnxk_tim_bkt_dec_lock(bkt);
+ goto __retry;
+ }
+
+ if (cnxk_tim_bkt_get_nent(hbt_state) != 0)
+ hbt_state |= BIT_ULL(34);
if (!(hbt_state & BIT_ULL(34)) ||
@@ -374,4 +385,6 @@ __retry:
goto __retry;
}
+ } else {
+ cnxk_tim_bkt_wait_hbt(bkt);
}
}
@@ -413,5 +426,4 @@ __retry:
return -ENOMEM;
}
- *chunk = *pent;
if (cnxk_tim_bkt_fetch_lock(lock_sema)) {
do {
@@ -420,4 +432,5 @@ __retry:
} while (cnxk_tim_bkt_fetch_lock(lock_sema) - 1);
}
+ cnxk_tim_bkt_inc_nent(bkt);
rte_atomic_thread_fence(rte_memory_order_acquire);
mirr_bkt->current_chunk = (uintptr_t)chunk;
@@ -427,12 +440,12 @@ __retry:
chunk = (struct cnxk_tim_ent *)mirr_bkt->current_chunk;
chunk += tim_ring->nb_chunk_slots - rem;
- *chunk = *pent;
+ cnxk_tim_bkt_inc_nent(bkt);
}
+ *chunk = *pent;
tim->impl_opaque[0] = (uintptr_t)chunk;
tim->impl_opaque[1] = (uintptr_t)bkt;
- rte_atomic_store_explicit(&tim->state, RTE_EVENT_TIMER_ARMED, rte_memory_order_release);
- cnxk_tim_bkt_inc_nent(bkt);
- cnxk_tim_bkt_dec_lock_relaxed(bkt);
+ tim->state = RTE_EVENT_TIMER_ARMED;
+ cnxk_tim_bkt_dec_lock(bkt);
return 0;
@@ -481,23 +494,14 @@ __retry:
if (unlikely(cnxk_tim_bkt_get_hbt(lock_sema))) {
if (cnxk_tim_bkt_get_nent(lock_sema) != 0) {
- uint64_t hbt_state;
-#ifdef RTE_ARCH_ARM64
- asm volatile(PLT_CPU_FEATURE_PREAMBLE
- " ldxr %[hbt], [%[w1]] \n"
- " tbz %[hbt], 33, .Ldne%= \n"
- " sevl \n"
- ".Lrty%=: wfe \n"
- " ldxr %[hbt], [%[w1]] \n"
- " tbnz %[hbt], 33, .Lrty%=\n"
- ".Ldne%=: \n"
- : [hbt] "=&r"(hbt_state)
- : [w1] "r"((&bkt->w1))
- : "memory");
-#else
- do {
- hbt_state = rte_atomic_load_explicit(&bkt->w1,
- rte_memory_order_relaxed);
- } while (hbt_state & BIT_ULL(33));
-#endif
+ uint64_t hbt_state = cnxk_tim_bkt_wait_hbt(bkt);
+
+ if (cnxk_tim_bkt_get_nent(lock_sema) != 0 &&
+ cnxk_tim_bkt_get_nent(hbt_state) == 0) {
+ cnxk_tim_bkt_dec_lock(bkt);
+ goto __retry;
+ }
+
+ if (cnxk_tim_bkt_get_nent(hbt_state) != 0)
+ hbt_state |= BIT_ULL(34);
if (!(hbt_state & BIT_ULL(34)) ||
@@ -506,4 +510,6 @@ __retry:
goto __retry;
}
+ } else {
+ cnxk_tim_bkt_wait_hbt(bkt);
}
}
@@ -554,5 +560,5 @@ __retry:
if (unlikely(chunk == NULL)) {
- cnxk_tim_bkt_dec_lock_relaxed(bkt);
+ cnxk_tim_bkt_dec_lock(bkt);
rte_errno = ENOMEM;
tim[index]->state = RTE_EVENT_TIMER_ERROR;
@@ -576,5 +582,5 @@ __retry:
}
- cnxk_tim_bkt_dec_lock_relaxed(bkt);
+ cnxk_tim_bkt_dec_lock(bkt);
return nb_timers;
--
2.50.0
---
Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- - 2025-07-18 20:29:11.729382882 +0100
+++ 0018-event-cnxk-fix-missing-HW-state-checks.patch 2025-07-18 20:29:10.821906997 +0100
@@ -1 +1 @@
-From f77eb8f3c655a2573aed77bea122d98efc12edef Mon Sep 17 00:00:00 2001
+From 717b7326e4f851b09773171e9922fa0926b5d0a8 Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit f77eb8f3c655a2573aed77bea122d98efc12edef ]
+
@@ -10 +11,0 @@
-Cc: stable at dpdk.org
More information about the stable
mailing list