patch 'event/dlb2: fix dequeue with CQ depth <= 16' has been queued to stable release 23.11.5

[Xueming Li]

Hi,

FYI, your patch has been queued to stable release 23.11.5

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 08/10/25. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=3712f69908613ff983eca0ec51096b5323e34be0

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From 3712f69908613ff983eca0ec51096b5323e34be0 Mon Sep 17 00:00:00 2001
From: Pravin Pathak <pravin.pathak at intel.com>
Date: Wed, 18 Jun 2025 23:03:10 -0500
Subject: [PATCH] event/dlb2: fix dequeue with CQ depth <= 16
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit 0b92203cdae06dee0626e46e62b9c34450e776d8 ]

When application configures a DIR port with CQ depth less than 8, DLB PMD
sets port's cq_depth as 8 and token reservation is used to make the
effective cq_depth smaller. However, while setting port's cq_depth_mask
application configured CQ depth was used resulting in reading incorrect
cachelines while dequeuing. Use PMD calculated CQ depth for cq_depth_mask
calculation.

Fixes: 3a6d0c04e7fb3e ("event/dlb2: add port setup")
Cc: stable at dpdk.org

Signed-off-by: Pravin Pathak <pravin.pathak at intel.com>
Signed-off-by: Tirthendu Sarkar <tirthendu.sarkar at intel.com>
---
 drivers/event/dlb2/dlb2.c       | 4 ++--
 drivers/event/dlb2/pf/dlb2_pf.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c
index cb25be6959..b252e9cac8 100644
--- a/drivers/event/dlb2/dlb2.c
+++ b/drivers/event/dlb2/dlb2.c
@@ -1858,9 +1858,9 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,
 	qm_port->cq_idx_unmasked = 0;
 
 	if (dlb2->poll_mode == DLB2_CQ_POLL_MODE_SPARSE)
-		qm_port->cq_depth_mask = (cfg.cq_depth * 4) - 1;
+		qm_port->cq_depth_mask = (qm_port->cq_depth * 4) - 1;
 	else
-		qm_port->cq_depth_mask = cfg.cq_depth - 1;
+		qm_port->cq_depth_mask = qm_port->cq_depth - 1;
 
 	qm_port->gen_bit_shift = rte_popcount32(qm_port->cq_depth_mask);
 	/* starting value of gen bit - it toggles at wrap time */
diff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c
index 019e90f7e7..3ce8178135 100644
--- a/drivers/event/dlb2/pf/dlb2_pf.c
+++ b/drivers/event/dlb2/pf/dlb2_pf.c
@@ -400,7 +400,7 @@ dlb2_pf_dir_port_create(struct dlb2_hw_dev *handle,
 	/* Calculate the port memory required, and round up to the nearest
 	 * cache line.
 	 */
-	alloc_sz = cfg->cq_depth * qe_sz;
+	alloc_sz = RTE_MAX(cfg->cq_depth, DLB2_MIN_HARDWARE_CQ_DEPTH) * qe_sz;
 	alloc_sz = RTE_CACHE_LINE_ROUNDUP(alloc_sz);
 
 	port_base = dlb2_alloc_coherent_aligned(&mz, &cq_base, alloc_sz,
-- 
2.34.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2025-07-30 22:50:04.065310440 +0800
+++ 0015-event-dlb2-fix-dequeue-with-CQ-depth-16.patch	2025-07-30 22:50:03.028756723 +0800
@@ -1 +1 @@
-From 0b92203cdae06dee0626e46e62b9c34450e776d8 Mon Sep 17 00:00:00 2001
+From 3712f69908613ff983eca0ec51096b5323e34be0 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit 0b92203cdae06dee0626e46e62b9c34450e776d8 ]
@@ -24 +27 @@
-index 08291b10b8..bec1e88074 100644
+index cb25be6959..b252e9cac8 100644
@@ -27 +30 @@
-@@ -1951,9 +1951,9 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,
+@@ -1858,9 +1858,9 @@ dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,
@@ -40 +43 @@
-index ac432b81ad..cd2788c035 100644
+index 019e90f7e7..3ce8178135 100644
@@ -43 +46 @@
-@@ -427,7 +427,7 @@ dlb2_pf_dir_port_create(struct dlb2_hw_dev *handle,
+@@ -400,7 +400,7 @@ dlb2_pf_dir_port_create(struct dlb2_hw_dev *handle,