patch 'common/cnxk: fix CQ tail drop' has been queued to stable release 23.11.5

[Xueming Li]

Hi,

FYI, your patch has been queued to stable release 23.11.5

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 06/28/25. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=589cb58bb089e8287dcaf43b9e1421aaa7716504

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From 589cb58bb089e8287dcaf43b9e1421aaa7716504 Mon Sep 17 00:00:00 2001
From: Nithin Dabilpuram <ndabilpuram at marvell.com>
Date: Wed, 28 May 2025 17:21:16 +0530
Subject: [PATCH] common/cnxk: fix CQ tail drop
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit dc8f10bb36bbd9dd961e4baba693181add66c962 ]

CQ tail drop feature is currently supposed to be enabled
when inline IPsec is disabled. But since XQE drop is not
enabled, CQ tail drop is implicitly disabled. Fix the same.

Fixes: c8c967e11717 ("common/cnxk: support enabling AURA tail drop for RQ")

Signed-off-by: Nithin Dabilpuram <ndabilpuram at marvell.com>
---
 drivers/common/cnxk/roc_nix.h       |  2 ++
 drivers/common/cnxk/roc_nix_queue.c | 11 +++++++++--
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 250d710c07..3d507cace7 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -354,6 +354,8 @@ struct roc_nix_rq {
 	bool lpb_drop_ena;
 	/* SPB aura drop enable */
 	bool spb_drop_ena;
+	/* XQE drop enable */
+	bool xqe_drop_ena;
 	/* End of Input parameters */
 	struct roc_nix *roc_nix;
 	uint64_t meta_aura_handle;
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index f96d5c3a96..4ffc3a70da 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -368,7 +368,7 @@ nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints,
 	aq->rq.rq_int_ena = 0;
 	/* Many to one reduction */
 	aq->rq.qint_idx = rq->qid % qints;
-	aq->rq.xqe_drop_ena = 1;
+	aq->rq.xqe_drop_ena = rq->xqe_drop_ena;
 
 	/* If RED enabled, then fill enable for all cases */
 	if (rq->red_pass && (rq->red_pass >= rq->red_drop)) {
@@ -452,6 +452,7 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
 		aq->rq.wqe_skip = rq->wqe_skip;
 		aq->rq.wqe_caching = 1;
 
+		aq->rq.xqe_drop_ena = 0;
 		aq->rq.good_utag = rq->tag_mask >> 24;
 		aq->rq.bad_utag = rq->tag_mask >> 24;
 		aq->rq.ltag = rq->tag_mask & BITMASK_ULL(24, 0);
@@ -471,6 +472,8 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
 		aq->rq.bad_utag = rq->tag_mask >> 24;
 		aq->rq.ltag = rq->tag_mask & BITMASK_ULL(24, 0);
 		aq->rq.cq = rq->cqid;
+		if (rq->xqe_drop_ena)
+			aq->rq.xqe_drop_ena = 1;
 	}
 
 	if (rq->ipsech_ena) {
@@ -519,7 +522,6 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
 	aq->rq.rq_int_ena = 0;
 	/* Many to one reduction */
 	aq->rq.qint_idx = rq->qid % qints;
-	aq->rq.xqe_drop_ena = 0;
 	aq->rq.lpb_drop_ena = rq->lpb_drop_ena;
 	aq->rq.spb_drop_ena = rq->spb_drop_ena;
 
@@ -564,6 +566,7 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
 			aq->rq_mask.bad_utag = ~aq->rq_mask.bad_utag;
 			aq->rq_mask.ltag = ~aq->rq_mask.ltag;
 			aq->rq_mask.cq = ~aq->rq_mask.cq;
+			aq->rq_mask.xqe_drop_ena = ~aq->rq_mask.xqe_drop_ena;
 		}
 
 		if (rq->ipsech_ena)
@@ -675,6 +678,10 @@ roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)
 	rq->roc_nix = roc_nix;
 	rq->tc = ROC_NIX_PFC_CLASS_INVALID;
 
+	/* Enable XQE/CQ drop on cn10k to count pkt drops only when inline is disabled */
+	if (roc_model_is_cn10k() && !roc_nix_inl_inb_is_enabled(roc_nix))
+		rq->xqe_drop_ena = true;
+
 	if (is_cn9k)
 		rc = nix_rq_cn9k_cfg(dev, rq, nix->qints, false, ena);
 	else
-- 
2.34.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2025-06-26 19:59:20.048455733 +0800
+++ 0059-common-cnxk-fix-CQ-tail-drop.patch	2025-06-26 19:59:17.442418042 +0800
@@ -1 +1 @@
-From dc8f10bb36bbd9dd961e4baba693181add66c962 Mon Sep 17 00:00:00 2001
+From 589cb58bb089e8287dcaf43b9e1421aaa7716504 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit dc8f10bb36bbd9dd961e4baba693181add66c962 ]
@@ -11 +13,0 @@
-Cc: stable at dpdk.org
@@ -20 +22 @@
-index 80392e7e1b..1e543d8f11 100644
+index 250d710c07..3d507cace7 100644
@@ -23 +25 @@
-@@ -355,6 +355,8 @@ struct roc_nix_rq {
+@@ -354,6 +354,8 @@ struct roc_nix_rq {
@@ -33 +35 @@
-index e852211ba4..39bd051c94 100644
+index f96d5c3a96..4ffc3a70da 100644
@@ -36 +38 @@
-@@ -530,7 +530,7 @@ nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints,
+@@ -368,7 +368,7 @@ nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints,
@@ -45 +47 @@
-@@ -613,6 +613,7 @@ nix_rq_cn10k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cf
+@@ -452,6 +452,7 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
@@ -53 +55 @@
-@@ -632,6 +633,8 @@ nix_rq_cn10k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cf
+@@ -471,6 +472,8 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
@@ -62 +64 @@
-@@ -680,7 +683,6 @@ nix_rq_cn10k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cf
+@@ -519,7 +522,6 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
@@ -70 +72 @@
-@@ -725,6 +727,7 @@ nix_rq_cn10k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cf
+@@ -564,6 +566,7 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
@@ -78 +80 @@
-@@ -950,6 +953,10 @@ roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)
+@@ -675,6 +678,10 @@ roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)
@@ -88 +90 @@
- 	else if (roc_model_is_cn10k())
+ 	else