patch 'net/hns3: check requirement for hardware GRO' has been queued to stable release 23.11.5

[Xueming Li]

Hi,

FYI, your patch has been queued to stable release 23.11.5

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 06/28/25. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=b779239d616c0adf67eb23fd41f7ad78cfceb877

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From b779239d616c0adf67eb23fd41f7ad78cfceb877 Mon Sep 17 00:00:00 2001
From: Dengdui Huang <huangdengdui at huawei.com>
Date: Mon, 9 Jun 2025 21:06:49 +0800
Subject: [PATCH] net/hns3: check requirement for hardware GRO
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit ae68b5d91c632a1dde839123f27b0317cf094170 ]

The HIP08 platform requires that data address be 64-byte aligned
for the GRO feature.

Most applications already use 64-byte aligned. So a check is added
to avoid using the GRO function when 64-byte aligned is used.

Fixes: d14c995b775a ("net/hns3: check Rx DMA address alignmnent")

Signed-off-by: Dengdui Huang <huangdengdui at huawei.com>
---
 drivers/net/hns3/hns3_rxtx.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c
index 58aa6edff4..1fb34e286d 100644
--- a/drivers/net/hns3/hns3_rxtx.c
+++ b/drivers/net/hns3/hns3_rxtx.c
@@ -276,12 +276,25 @@ hns3_free_all_queues(struct rte_eth_dev *dev)
 static int
 hns3_check_rx_dma_addr(struct hns3_hw *hw, uint64_t dma_addr)
 {
+	uint64_t rx_offload = hw->data->dev_conf.rxmode.offloads;
 	uint64_t rem;
 
 	rem = dma_addr & (hw->rx_dma_addr_align - 1);
 	if (rem > 0) {
-		hns3_err(hw, "The IO address of the beginning of the mbuf data "
-			 "must be %u-byte aligned", hw->rx_dma_addr_align);
+		hns3_err(hw,
+			 "mbuf DMA address must be %u-byte aligned",
+			 hw->rx_dma_addr_align);
+		return -EINVAL;
+	}
+
+	/*
+	 * This check is for HIP08 network engine. The GRO function
+	 * requires that mbuf DMA address is 64-byte aligned.
+	 */
+	rem = dma_addr & (HNS3_RX_DMA_ADDR_ALIGN_128 - 1);
+	if ((rx_offload & RTE_ETH_RX_OFFLOAD_TCP_LRO) && rem > 0) {
+		hns3_err(hw,
+			 "GRO requires that mbuf DMA address be 64-byte aligned");
 		return -EINVAL;
 	}
 	return 0;
-- 
2.34.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2025-06-26 19:59:20.812153701 +0800
+++ 0083-net-hns3-check-requirement-for-hardware-GRO.patch	2025-06-26 19:59:17.526418038 +0800
@@ -1 +1 @@
-From ae68b5d91c632a1dde839123f27b0317cf094170 Mon Sep 17 00:00:00 2001
+From b779239d616c0adf67eb23fd41f7ad78cfceb877 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit ae68b5d91c632a1dde839123f27b0317cf094170 ]
@@ -13 +15,0 @@
-Cc: stable at dpdk.org
@@ -21 +23 @@
-index bde46733b0..f9fde3948a 100644
+index 58aa6edff4..1fb34e286d 100644
@@ -24 +26 @@
-@@ -281,12 +281,25 @@ hns3_free_all_queues(struct rte_eth_dev *dev)
+@@ -276,12 +276,25 @@ hns3_free_all_queues(struct rte_eth_dev *dev)