[PATCH 01/10] net/e1000/base: refactor K1 exit timeout configuration

[Ciara Loftus]

From: Vitaly Lifshits <vitaly.lifshits at intel.com>

Replace magic numbers in the FEXTNVM12 register access with named bit
definitions to improve readability. Add a missing error path to ensure
ME activity blocking a PHY reset is correctly propagated to the caller.
Also improve some code formatting.

Fixes: 38db3f7f50bd ("e1000: update base driver")
Cc: stable at dpdk.org

Signed-off-by: Vitaly Lifshits <vitaly.lifshits at intel.com>
Signed-off-by: Ciara Loftus <ciara.loftus at intel.com>
---
 drivers/net/intel/e1000/base/e1000_ich8lan.c | 11 ++++++++---
 drivers/net/intel/e1000/base/e1000_ich8lan.h |  3 +++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/net/intel/e1000/base/e1000_ich8lan.c b/drivers/net/intel/e1000/base/e1000_ich8lan.c
index ece61650f7..58597cce8a 100644
--- a/drivers/net/intel/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/intel/e1000/base/e1000_ich8lan.c
@@ -305,8 +305,8 @@ STATIC s32 e1000_reconfigure_k1_exit_timeout(struct e1000_hw *hw)
 		return E1000_SUCCESS;
 
 	fextnvm12 = E1000_READ_REG(hw, E1000_FEXTNVM12);
-	fextnvm12 |= (1 << 23);
-	fextnvm12 &= ~((1 << 22));
+	fextnvm12 &= ~E1000_FEXTNVM12_PHYPD_CTRL_MASK;
+	fextnvm12 |= E1000_FEXTNVM12_PHYPD_CTRL_P1;
 	E1000_WRITE_REG(hw, E1000_FEXTNVM12, fextnvm12);
 
 	msec_delay_irq(1);
@@ -318,6 +318,9 @@ STATIC s32 e1000_reconfigure_k1_exit_timeout(struct e1000_hw *hw)
 	ret_val = hw->phy.ops.write_reg_locked(hw, E1000_PHY_TIMEOUTS_REG,
 					       phy_timeout);
 
+	DEBUGOUT1("e1000_reconfigure_k1_exit_timeout returns %d\n",
+		  ret_val);
+
 	return ret_val;
 }
 
@@ -460,8 +463,10 @@ STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 		 *  the PHY is in.
 		 */
 		ret_val = hw->phy.ops.check_reset_block(hw);
-		if (ret_val)
+		if (ret_val) {
 			ERROR_REPORT("ME blocked access to PHY after reset\n");
+			goto out;
+		}
 
 		if (hw->mac.type >= e1000_pch_mtp) {
 			ret_val = hw->phy.ops.acquire(hw);
diff --git a/drivers/net/intel/e1000/base/e1000_ich8lan.h b/drivers/net/intel/e1000/base/e1000_ich8lan.h
index f2ba910ea6..43360400bc 100644
--- a/drivers/net/intel/e1000/base/e1000_ich8lan.h
+++ b/drivers/net/intel/e1000/base/e1000_ich8lan.h
@@ -89,6 +89,9 @@
 #define E1000_FEXTNVM11_DISABLE_PB_READ		0x00000200
 #define E1000_FEXTNVM11_DISABLE_MULR_FIX	0x00002000
 #define E1000_FEXTNVM12_DONT_WAK_DPG_CLKREQ	0x00001000
+#define E1000_FEXTNVM12_PHYPD_CTRL_MASK		0x00C00000
+#define E1000_FEXTNVM12_PHYPD_CTRL_P1		0x00800000
+
 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
 #define E1000_RXDCTL_THRESH_UNIT_DESC	0x01000000
 
-- 
2.43.0