patch 'net/gve: add cacheline overlap margin to DQO Tx ring' has been queued to stable release 24.11.9

[luca.boccassi at gmail.com]

Hi,

FYI, your patch has been queued to stable release 24.11.9

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 11/07/26. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/bluca/dpdk-stable

This queued commit can be viewed at:
https://github.com/bluca/dpdk-stable/commit/01016c44c4320e6eb03807db81376fe39f8d716a

Thanks.

Luca Boccassi

---
>From 01016c44c4320e6eb03807db81376fe39f8d716a Mon Sep 17 00:00:00 2001
From: Tathagat Priyadarshi <tathagat.dpdk at gmail.com>
Date: Fri, 16 Oct 2026 17:45:40 +0000
Subject: [PATCH] net/gve: add cacheline overlap margin to DQO Tx ring

[ upstream commit 7ae98ca0bf70f9e7537c667d8dbd06d999c46741 ]

The GVNIC DQO hardware DMA engine prefetches descriptors in cacheline
units (64 bytes = 4 descriptors of 16 bytes each). When producer tail
and consumer head indices share a cacheline, CPU and device DMA memory
collisions can occur.

Align with the Linux driver (gve_has_tx_slots_available()) by requiring
GVE_TX_MIN_DESC_PREVENT_CACHE_OVERLAP (4 descriptors) headroom when
checking descriptor availability before enqueueing packets.

Fixes: 4022f9999f56 ("net/gve: support basic Tx data path for DQO")

Signed-off-by: Tathagat Priyadarshi <tathagat.dpdk at gmail.com>
Acked-by: Joshua Washington <joshwash at google.com>
---
 drivers/net/gve/gve_tx_dqo.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c
index 33b9b700efd..c09087ee4a8 100644
--- a/drivers/net/gve/gve_tx_dqo.c
+++ b/drivers/net/gve/gve_tx_dqo.c
@@ -180,6 +180,7 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 	uint16_t last_re_interval;
 	uint16_t last_desc_idx;
 	uint16_t first_sw_id;
+	uint16_t req_descs;
 	const char *reason;
 	uint16_t nb_tx = 0;
 	uint64_t ol_flags;
@@ -220,14 +221,17 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 
 		nb_descs = gve_tx_pkt_nb_data_descs(tx_pkt);
 		nb_descs += tso;
+		req_descs = nb_descs + GVE_TX_MIN_DESC_PREVENT_CACHE_OVERLAP;
 
-		/* Clean if there aren't enough descriptors to send the packet. */
-		if (unlikely(txq->nb_free < nb_descs)) {
+		/* Clean if there aren't enough descriptors to send the packet
+		 * while maintaining the cacheline overlap margin.
+		 */
+		if (unlikely(txq->nb_free < req_descs)) {
 			int nb_to_clean = RTE_MAX(DQO_TX_MULTIPLIER * txq->rs_thresh,
-						  nb_descs);
+						  (int)req_descs);
 
 			gve_tx_clean_descs_dqo(txq, nb_to_clean);
-			if (txq->nb_free < nb_descs)
+			if (txq->nb_free < req_descs)
 				break;
 		}
 
-- 
2.47.3

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2026-11-05 16:42:48.271356996 +0000
+++ 0087-net-gve-add-cacheline-overlap-margin-to-DQO-Tx-ring.patch	2026-11-05 16:42:45.021063775 +0000
@@ -1 +1 @@
-From 7ae98ca0bf70f9e7537c667d8dbd06d999c46741 Mon Sep 17 00:00:00 2001
+From 01016c44c4320e6eb03807db81376fe39f8d716a Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit 7ae98ca0bf70f9e7537c667d8dbd06d999c46741 ]
+
@@ -16 +17,0 @@
-Cc: stable at dpdk.org
@@ -25 +26 @@
-index 55187fec71..637632ce4d 100644
+index 33b9b700efd..c09087ee4a8 100644
@@ -28,4 +29,4 @@
-@@ -256,6 +256,7 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
- 	struct gve_tx_pkt *pkts;
- 	struct rte_mbuf *tx_pkt;
- 	uint16_t compl_tag;
+@@ -180,6 +180,7 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
+ 	uint16_t last_re_interval;
+ 	uint16_t last_desc_idx;
+ 	uint16_t first_sw_id;
@@ -35,2 +36,2 @@
- 	uint64_t bytes = 0;
-@@ -288,14 +289,17 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
+ 	uint64_t ol_flags;
+@@ -220,14 +221,17 @@ gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
@@ -43 +44 @@
--		if (unlikely(!gve_can_tx(txq, nb_descs, 1))) {
+-		if (unlikely(txq->nb_free < nb_descs)) {
@@ -47 +48 @@
-+		if (unlikely(!gve_can_tx(txq, req_descs, 1))) {
++		if (unlikely(txq->nb_free < req_descs)) {
@@ -53,2 +54,2 @@
--			if (!gve_can_tx(txq, nb_descs, 1))
-+			if (!gve_can_tx(txq, req_descs, 1))
+-			if (txq->nb_free < nb_descs)
++			if (txq->nb_free < req_descs)