|SUCCESS| eal/x86: fix LZCNT CPU feature bit

[dpdklab at iol.unh.edu]

Test-Label: ai-code-review
Test-Status: SUCCESS
https://dpdk.org/patch/168612

_AI Code Review_

=== Patch Review: series.patch (via Claude) ===
Review date: 2026-08-28

# DPDK Patch Review

## Summary
This patch fixes a critical correctness bug in x86 CPU feature detection. The LZCNT flag was being tested against the wrong CPUID bit (ECX[4] instead of ECX[5]), causing incorrect feature reporting. The fix is simple, correct, and properly tagged for stable backport.

## Findings

### Errors
None.

### Warnings
None.

### Info

**LZCNT bit correction is correct**

The patch correctly changes the LZCNT feature bit from ECX[4] to ECX[5] in CPUID function 0x80000001h. According to Intel and AMD documentation:
- ECX[5]: LZCNT (Leading Zero Count) instruction support
- ECX[4]: CR8 in legacy mode (AMD-specific, reserved on Intel)

The change aligns with the official x86 CPUID specifications from both vendors.

**Mailmap entry follows conventions**

The `.mailmap` entry is correctly formatted and alphabetically placed.

**Commit tagging is appropriate**

- `Fixes:` tag references the initial commit where this bug was introduced
- `Cc: stable at dpdk.org` correctly marks this for LTS backport
- The fix is minimal and self-contained, suitable for stable branches

**No other code uses the broken flag directly**

The impact is limited to feature detection. DPDK code that checks `RTE_CPUFLAG_LZCNT` via `rte_cpu_get_flag_enabled()` will now report correctly. No other code changes are needed because the flag is only used for capability queries, not as a build-time constant.

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## Overall Assessment

**APPROVED** - This is a straightforward correctness fix with no style, API, or process issues. The patch is ready for merge and should be backported to stable branches as indicated by the `Cc: stable at dpdk.org` tag.