|WARNING| [RFC, 32/32] doc: update release notes about rte_smp_XX removal

[dpdklab at iol.unh.edu]

Test-Label: ai-code-review
Test-Status: WARNING
https://dpdk.org/patch/167036

_AI Code Review_

=== Patch Review: series.patch (via Claude) ===
Review date: 2026-07-30

# DPDK Patch Review

## Summary
This patch series removes deprecated `rte_smp_*mb()` barriers from DPDK, replacing them with C11 atomic fences and operations. The series contains 32 patches converting various subsystems.

---

## Patch 1: bpf: replace deprecated SMP barriers with C11 fences

**Errors:**

None.

**Warnings:**

None.

**Info:**

The conversion looks correct. The use counter handshake becomes seq_cst fences (matching the full barrier semantics), and the read barrier in unuse becomes acquire. The relaxed load/store avoids the unnecessary seq_cst atomic add per burst.

---

## Patch 2: test: remove test for rte_smp_mb

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct removal of obsolete test for deprecated API.

---

## Patch 3: bus/vmbus: fix ring buffer ordering on weakly ordered CPUs

**Errors:**

The barrier in `vmbus_rxbr_read()` orders the data copy before the read index update. The cast to `volatile uint32_t __rte_atomic *` is correct for the release store. However, the justification in the comment may be incomplete: on x86 TSO provides the necessary ordering for free, but on ARM the release is required. The patch is correct.

**Warnings:**

None.

**Info:**

The full fence in `rte_vmbus_chan_signal_tx()` is correct -- it orders the earlier ring index update (a store) against the load of the host interrupt mask. A write barrier does not order store against load; seq_cst fence is needed.

---

## Patch 4: bus/vmbus: fix missing acquire on receive ring index

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct addition of acquire load on the write index. The control dependency from the comparison does not order load against load on weakly ordered CPUs; acquire is needed.

---

## Patch 5: bus/vmbus: replace SMP barriers with C11 atomics

**Errors:**

None.

**Warnings:**

None.

**Info:**

The full barriers become seq_cst fences; read barriers become acquire. The write barrier before publishing the transmit index becomes a release fence. The comment notes that the following cmpset is a full barrier today, but the fence ensures correctness when cmpset is later converted to release ordering.

---

## Patch 6: baseband: convert rte_smp_rmb to fence

**Errors:**

None.

**Warnings:**

None.

**Info:**

Straightforward conversion. The barriers ensure the DMA response is read atomically before processing.

---

## Patch 7: net/hinic: replace rte_smp_rmb

**Errors:**

None.

**Warnings:**

None.

**Info:**

Simple acquire fence conversions in control path mailbox code.

---

## Patch 8: net/intel: replace rte_smp_rmb

**Errors:**

None.

**Warnings:**

None.

**Info:**

Acquire fences after reading descriptor status bits. Standard Rx descriptor polling pattern.

---

## Patch 9: crypto_caam_jr: replace rte_smp_rmb

**Errors:**

None.

**Warnings:**

None.

**Info:**

Acquire fence before processing job ring responses.

---

## Patch 10: net/virtio: replace rte_smp_rmb

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct conversion. The x86 special case remains a compiler barrier (now expressed as a release fence), preserving the measured performance characteristic. The comment is updated to reflect the new construct.

---

## Patch 11: net/thunderx: replace rte_smp_rmb

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct redefinition of the `nicvf_smp_rmb()` wrapper as an acquire fence.

---

## Patch 12: stack: always use C11 memory model implementation

**Errors:**

None.

**Warnings:**

None.

**Info:**

The removal of the generic implementation is justified: the only difference is memory ordering, and the C11 version uses the correct (weaker) ordering. The comment notes that x86 and ThunderX used the generic version, and the C11 version generates equivalent or better code on both.

---

## Patch 13: ring: replace SMP read barrier with C11 acquire fence

**Errors:**

None.

**Warnings:**

None.

**Info:**

The conversion is correct. The comment is updated to reflect that it's now an acquire fence, not an SMP read barrier. The justification for keeping the gcc implementation (measured performance difference) is noted.

---

## Patch 14: crypto/virtio: update comment reference to rte_smp_rmb

**Errors:**

None.

**Warnings:**

None.

**Info:**

Documentation fix. The comment now refers to `virtio_rmb` instead of `rte_smp_rmb`.

---

## Patch 15: event/sw: fix unlinks in progress counter races

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct fix. The atomic counter operations prevent lost increments and ensure proper ordering. The acquire exchange on the scheduler side pairs with the release fetch-add on unlink.

---

## Patch 16: event/sw: replace SMP barriers with C11 atomics

**Errors:**

None.

**Warnings:**

None.

**Info:**

Release stores for cq map count, port initialized, and device started. The release fence after clearing started is correct. The comment notes that the cq map count reads stay plain loads and explains the transient window is pre-existing.

---

## Patch 17: eal/x86: move optimized fence out of SMP barrier

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct refactoring. The lock add optimization moves into `rte_atomic_thread_fence()` and `rte_smp_mb()` becomes a wrapper. This preserves the optimization while inverting the dependency, making the deprecated barrier removal a pure deletion later.

---

## Patch 18: common/octeontx: remove redundant barrier in mbox

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct removal. `rte_write64()` begins with `rte_io_wmb()`, so the explicit SMP write barrier is redundant.

---

## Patch 19: crypto/caam_jr: use IO barrier before job ring doorbell

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct conversion. The barrier orders DMA memory writes against MMIO doorbell write, which is device ordering requiring `rte_io_wmb()`, not SMP ordering. The original SMP barrier was insufficient on ARM (inner shareable domain does not order against the device).

---

## Patch 20: crypto/octeontx: use IO barrier before doorbell

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct conversion to IO barrier. The doorbell is written with `rte_write64_relaxed()`, so the barrier must order against the device.

---

## Patch 21: mempool/octeontx: use IO barrier in pool destroy

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct conversion. The barrier flushes outstanding writes to the FPA pool before teardown, which is device ordering. Control path.

---

## Patch 22: event/octeontx: replace deprecated SMP barriers

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct conversions. Worker barriers become IO write barriers (ordering event payload writes before device operations). Selftest barriers become release fences (publishing worker parameters before lcore launch).

---

## Patch 23: event/dpaa2: replace deprecated barrier in selftest

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct release fence conversions for publishing worker parameters before lcore launch.

---

## Patch 24: event/dsw: replace SMP barriers with release fences

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct conversion. All four barriers publish flow table or ring updates before control message enqueue, which is release ordering. The comment notes the fences may be removable because `rte_ring` producer tail update is itself a release store.

---

## Patch 25: event/opdl: replace SMP barriers with C11 atomics

**Errors:**

None.

**Warnings:**

None.

**Info:**

Release store for port configured flag and release fence after clearing started. Both control path.

---

## Patch 26: net/netvsc: replace SMP barrier in RNDIS response

**Errors:**

None.

**Warnings:**

None.

**Info:**

Release fence for publishing the copied response before clearing the pending id. The comment correctly notes that the following cmpset is a full barrier today, but the explicit fence preserves correctness when cmpset is later converted to release.

---

## Patch 27: net/thunderx: replace deprecated SMP barriers

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct conversions. RBDR refill barrier becomes IO write barrier (ordering descriptor writes before doorbell). Mailbox barriers become release/acquire fences.

---

## Patch 28: net/virtio: replace deprecated barrier in avail index update

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct conversion. The x86 special case preserves its shape: a release fence is the same compiler barrier the SMP write barrier was, so the measured performance reason for the branch is preserved.

---

## Patch 29: eal: remove stale SMP barrier in rte_service

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct removal. The barrier pairs with nothing and is a leftover from the C11 atomics conversion.

---

## Patch 30: eal: remove rte_smp_XX

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct removal of deprecated and now-unused functions. All platforms updated.

---

## Patch 31: checkpatches: no longer warn about rte_smp_XX

**Errors:**

None.

**Warnings:**

None.

**Info:**

Correct. The deprecated check is removed; new uses will be detected as compile errors.

---

## Patch 32: doc: update release notes about rte_smp_XX removal

**Errors:**

None.

**Warnings:**

The replacement guidance should mention that `rte_smp_wmb()` does not have a single mechanical replacement: depending on the use case, it may be a release fence, a release store, or a sequence of release stores. The current text "revised code to use `rte_atomic_load/store`" is vague.

**Info:**

Suggest:

```
* ``rte_smp_wmb()`` replaced with ``rte_atomic_thread_fence(rte_memory_order_release)`` for publish patterns, or converted to release stores (``rte_atomic_store_explicit(..., rte_memory_order_release)``) where appropriate.
```

---

## Overall Assessment

This is a large, well-executed series. The conversions are correct, and the commits are organized logically. The series successfully removes the deprecated SMP barriers and replaces them with appropriate C11 constructs. The performance-critical optimizations (x86 lock add, x86 virtio special case) are preserved. The fixes for existing ordering bugs (vmbus, event/sw) are valuable.

**No blocking errors identified.** One documentation warning on the final patch.