|WARNING| event/cnxk: fix TIM HWWQE handling and chunk alignment

[dpdklab at iol.unh.edu]

Test-Label: ai-code-review
Test-Status: WARNING
https://dpdk.org/patch/171478

_AI Code Review_

=== Patch Review: series.patch (via Claude) ===
Review date: 2026-10-16

# DPDK Patch Review

## Errors

None identified.

## Warnings

**W1: Missing release notes**

The patch fixes critical bugs (incorrect HWWQE enablement logic, wrong error state mapping, insufficient alignment handling) but does not update the release notes in `doc/guides/rel_notes/`. Fixes of this nature should be documented.

**W2: Unconventional division by macro result**

Line 325 in `cnxk_tim_evdev.c`:
```c
tim_ring->nb_chunks = RTE_MAX(RTE_ALIGN_MUL_CEIL(tim_ring->nb_timers,
		CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz)) /
		CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz), 1UL);
```

Dividing by `CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz)` immediately after using it in `RTE_ALIGN_MUL_CEIL` is correct mathematically (rounds up `nb_timers` to a multiple of the chunk slot count, then divides to get the number of chunks). However, it would be clearer to use `RTE_ALIGN_DIV_CEIL` if available, or to add a comment explaining the rounding-up division. The pattern is valid but could be expressed more directly.

## Info

**I1: Code simplification opportunity**

Lines 704-707 in `cnxk_tim_worker.h`:
```c
switch (rsp) {
case 0x3:
	for (j = 0; j < CNXK_TIM_ENT_PER_LMT; j++)
		tim[(i * CNXK_TIM_ENT_PER_LMT) + j]->state =
			RTE_EVENT_TIMER_ERROR_TOOLATE;
	done -= CNXK_TIM_ENT_PER_LMT;
	break;
case 0x4:
	for (j = 0; j < CNXK_TIM_ENT_PER_LMT; j++)
		tim[(i * CNXK_TIM_ENT_PER_LMT) + j]->state =
			RTE_EVENT_TIMER_ERROR_TOOEARLY;
	done -= CNXK_TIM_ENT_PER_LMT;
	break;
```

The cases 0x3 and 0x4 differ only in the error state assigned. A helper or a more compact pattern could reduce repetition. However, this is a pre-existing style and the fix is correct.

**I2: Magic number `0xF0` and `0x10`/`0x50`**

Lines 713-715, 770-772 in `cnxk_tim_worker.h`:
```c
uint64_t res = rte_atomic_load_explicit(
	(uint64_t __rte_atomic *)&t->impl_opaque[0],
	rte_memory_order_relaxed) & 0xF0;

if (res != 0x10 && res != 0x50) {
```

The patch adds `0x50` to the check (previously only checked `!= 0x10`), matching the new acceptance of `rsp == 0x5` at line 695/752. The bit pattern meanings (`0xF0` mask, `0x10`/`0x50` success values) are undocumented. Adding symbolic constants or a comment would improve clarity. This is pre-existing style, and the patch correctly updates both the response check and the per-timer state check to be consistent.

Review-Result: WARNING