|WARNING| [v3] common/mlx5: fix mkey ordering enum

[dpdklab at iol.unh.edu]

Test-Label: ai-code-review
Test-Status: WARNING
https://dpdk.org/patch/172084

_AI Code Review_

=== Patch Review: series.patch (via Claude) ===
Review date: 2026-10-26

# DPDK Patch Review

## ERRORS

None.

## WARNINGS

**1. Missing release notes update**

This patch changes the interpretation of HCA capability flags and the conditions under which memory key ordering is applied on Windows. This is a behavioral change that affects how relaxed ordering is configured based on firmware capabilities. The release notes should document this change.

Suggested fix: Add an entry to `doc/guides/rel_notes/release_26_11.rst` (or the appropriate release) under the "Fixed Issues" section describing the corrected mkey ordering enum and the Windows-specific behavior change.

**2. Conditional logic may deserve a comment**

```c
if (!mlx5_haswell_broadwell_cpu) {
	mkey_attr.relaxed_ordering_write = attr.relaxed_ordering_write;
	mkey_attr.relaxed_ordering_read =
		attr.relaxed_ordering_read || attr.pci_relaxed_ordered_read;
	if (attr.mkc_order_write_after_write_ro_only)
		mlx5_devx_mkey_attr_set_ordering(&mkey_attr, &attr);
}
```

The nested conditional structure implementing the "relaxed-order-only mode" check is not immediately obvious. A brief comment explaining the firmware capability check would improve maintainability.

Suggested fix:
```c
if (!mlx5_haswell_broadwell_cpu) {
	mkey_attr.relaxed_ordering_write = attr.relaxed_ordering_write;
	mkey_attr.relaxed_ordering_read =
		attr.relaxed_ordering_read || attr.pci_relaxed_ordered_read;
	/* Apply read-after-write ordering only when firmware requires
	 * relaxed-order-only mode (mkc_order_write_after_write_ro_only set).
	 */
	if (attr.mkc_order_write_after_write_ro_only)
		mlx5_devx_mkey_attr_set_ordering(&mkey_attr, &attr);
}
```

## INFO

None.

---

The patch correctly addresses the enum mismatch with the updated device specification by removing the undefined `MLX5_MKC_RAW_ORDERING_SAO` value and adjusting `MLX5_MKC_RAW_ORDERING_RO` to 0x1. The Windows-specific logic change appears sound: relaxed-ordering flags are now always copied from HCA capabilities on non-Haswell CPUs, with read-after-write ordering applied conditionally based on the firmware's `mkc_order_write_after_write_ro_only` flag. This aligns the Windows driver behavior with other mlx5 drivers.

Review-Result: WARNING