|WARNING| [v3] common/mlx5: fix mkey ordering enum

[dpdklab at iol.unh.edu]

Test-Label: ai-code-review
Test-Status: WARNING
https://dpdk.org/patch/172084

_AI Code Review_

=== Patch Review: series.patch (via Claude) ===
Review date: 2026-10-26

# DPDK Patch Review

## Patch: common/mlx5: fix mkey ordering enum

### ERRORS

**Error 1: Missing `RTE_EXPORT_*` macro for new public symbols**

The patch modifies the `enum mlx5_mkc_raw_ordering` in `mlx5_prm.h`, removing `MLX5_MKC_RAW_ORDERING_SAO` and changing the value of `MLX5_MKC_RAW_ORDERING_RO` from `0x2` to `0x1`. This is an ABI change to a public enum.

However, examining the context: `drivers/common/mlx5/mlx5_prm.h` appears to be a driver-private header (mlx5 PMD internal definitions), not installed as part of the public DPDK API. Driver-private headers under `drivers/*/` do not constitute public ABI unless explicitly installed via meson.build.

**Correction:** Without access to `drivers/common/mlx5/meson.build`, I cannot verify if `mlx5_prm.h` is in the `headers` list. If it is not installed, this is not an ABI concern. Since this is driver-internal code and the enum values are being corrected to match hardware specification, and the change is marked with a `Fixes:` tag targeting stable, this appears to be a bug fix rather than an API change.

*Withdrawn - insufficient evidence to classify as Error.*

### WARNINGS

**Warning 1: Logic change without full verification of dependent code paths**

In `drivers/common/mlx5/windows/mlx5_common_os.c`, the patch changes the conditional logic for setting mkey ordering attributes:

**Original code:**
```c
if (!mlx5_haswell_broadwell_cpu)
	mlx5_devx_mkey_attr_set_ordering(&mkey_attr, &attr);
```

**New code:**
```c
if (!mlx5_haswell_broadwell_cpu) {
	mkey_attr.relaxed_ordering_write = attr.relaxed_ordering_write;
	mkey_attr.relaxed_ordering_read =
		attr.relaxed_ordering_read || attr.pci_relaxed_ordered_read;
	if (attr.mkc_order_write_after_write_ro_only)
		mlx5_devx_mkey_attr_set_ordering(&mkey_attr, &attr);
}
```

The new logic adds an **additional condition** `attr.mkc_order_write_after_write_ro_only` before calling `mlx5_devx_mkey_attr_set_ordering()`. This means on non-Haswell CPUs where `mkc_order_write_after_write_ro_only` is **not** set, the function `mlx5_devx_mkey_attr_set_ordering()` will **not** be called at all, whereas previously it was always called.

**Concern:** Without reading `mlx5_devx_mkey_attr_set_ordering()` implementation, I cannot verify what other fields it sets besides read-after-write ordering. If it sets additional fields beyond the two relaxed-ordering flags now set explicitly, those fields would be left uninitialized on systems where `mkc_order_write_after_write_ro_only == 0`.

**Suggested fix:** Verify that `mlx5_devx_mkey_attr_set_ordering()` only sets the read-after-write ordering field, or ensure all necessary fields are initialized in the new code path.

### INFO

None.

---

## Summary

The enum value correction aligns with the updated hardware specification and is appropriate for a stable backport. The Windows-specific logic change requires verification that all necessary mkey attributes are initialized when `mkc_order_write_after_write_ro_only` is not set.

Review-Result: WARNING