[dpdk-users] [dpdk-dev] Issue with DCB with X710 Quad 10Gb NIC

[Mike DeVico]

As suggested I tried the following:

I have an Intel FlexRAN FerryBridge broadcasting a packet 1/s which looks like the following
(sudo tcpdump -i p7p1 -xx):

        0x0000:  ffff ffff ffff 0000 aeae 0000 8100 4001
        0x0010:  0800 0009 0000 0000 0001 8086 3600 010f
        0x0020:  0000 0000 0000 0000 0000 0000 0000 0000
        0x0030:  0000 0000 0000 0000 0000 0000

The first 12 bytes are the dest/src MAC address followed by the 802.1Q Header (8100 4001)
If you crack this, the MS 16 bits are the TPID which is set to 8100 by the Ferrybridge. 
The next 16 bits (0x4001) make up the PCP bits [15:13], the DEI [12] and the VID [11:0]. So if you
crack the 0x4001 this makes the PCP 2 (010b), the DEI 0 and VID 1 (000000000001b).

Given this I expect the packets to but placed in Pool 1/Queue 2 (based on VID 1 and PCP 2). 
However, when I run:

./vmdq_dcb_app -w 0000:05:00.0 -w 0000:05:00.1 -l 1 -- -p 3 --nb-pools 16 --nb-tcs 8 --enable-rss
EAL: Detected 24 lcore(s)
EAL: Detected 2 NUMA nodes
EAL: Multi-process socket /var/run/dpdk/rte/mp_socket
EAL: Probing VFIO support...
EAL: PCI device 0000:05:00.0 on NUMA socket 0
EAL:   probe driver: 8086:1572 net_i40e
EAL: PCI device 0000:05:00.1 on NUMA socket 0
EAL:   probe driver: 8086:1572 net_i40e
vmdq queue base: 64 pool base 1
Configured vmdq pool num: 16, each vmdq pool has 8 queues
Port 0 modified RSS hash function based on hardware support,requested:0x3bffc configured:0x3ef8
Port 0 MAC: e8 ea 6a 27 b5 4d
Port 0 vmdq pool 0 set mac 52:54:00:12:00:00
Port 0 vmdq pool 1 set mac 52:54:00:12:00:01
Port 0 vmdq pool 2 set mac 52:54:00:12:00:02
Port 0 vmdq pool 3 set mac 52:54:00:12:00:03
Port 0 vmdq pool 4 set mac 52:54:00:12:00:04
Port 0 vmdq pool 5 set mac 52:54:00:12:00:05
Port 0 vmdq pool 6 set mac 52:54:00:12:00:06
Port 0 vmdq pool 7 set mac 52:54:00:12:00:07
Port 0 vmdq pool 8 set mac 52:54:00:12:00:08
Port 0 vmdq pool 9 set mac 52:54:00:12:00:09
Port 0 vmdq pool 10 set mac 52:54:00:12:00:0a
Port 0 vmdq pool 11 set mac 52:54:00:12:00:0b
Port 0 vmdq pool 12 set mac 52:54:00:12:00:0c
Port 0 vmdq pool 13 set mac 52:54:00:12:00:0d
Port 0 vmdq pool 14 set mac 52:54:00:12:00:0e
Port 0 vmdq pool 15 set mac 52:54:00:12:00:0f
vmdq queue base: 64 pool base 1
Configured vmdq pool num: 16, each vmdq pool has 8 queues
Port 1 modified RSS hash function based on hardware support,requested:0x3bffc configured:0x3ef8
Port 1 MAC: e8 ea 6a 27 b5 4e
Port 1 vmdq pool 0 set mac 52:54:00:12:01:00
Port 1 vmdq pool 1 set mac 52:54:00:12:01:01
Port 1 vmdq pool 2 set mac 52:54:00:12:01:02
Port 1 vmdq pool 3 set mac 52:54:00:12:01:03
Port 1 vmdq pool 4 set mac 52:54:00:12:01:04
Port 1 vmdq pool 5 set mac 52:54:00:12:01:05
Port 1 vmdq pool 6 set mac 52:54:00:12:01:06
Port 1 vmdq pool 7 set mac 52:54:00:12:01:07
Port 1 vmdq pool 8 set mac 52:54:00:12:01:08
Port 1 vmdq pool 9 set mac 52:54:00:12:01:09
Port 1 vmdq pool 10 set mac 52:54:00:12:01:0a
Port 1 vmdq pool 11 set mac 52:54:00:12:01:0b
Port 1 vmdq pool 12 set mac 52:54:00:12:01:0c
Port 1 vmdq pool 13 set mac 52:54:00:12:01:0d
Port 1 vmdq pool 14 set mac 52:54:00:12:01:0e
Port 1 vmdq pool 15 set mac 52:54:00:12:01:0f
Core 0(lcore 1) reading queues 64-191

<SIGHUP>

Pool 0: 0 0 0 0 0 0 0 0 
Pool 1: 119 0 0 0 0 0 0 0 
Pool 2: 0 0 0 0 0 0 0 0 
Pool 3: 0 0 0 0 0 0 0 0 
Pool 4: 0 0 0 0 0 0 0 0 
Pool 5: 0 0 0 0 0 0 0 0 
Pool 6: 0 0 0 0 0 0 0 0 
Pool 7: 0 0 0 0 0 0 0 0 
Pool 8: 0 0 0 0 0 0 0 0 
Pool 9: 0 0 0 0 0 0 0 0 
Pool 10: 0 0 0 0 0 0 0 0 
Pool 11: 0 0 0 0 0 0 0 0 
Pool 12: 0 0 0 0 0 0 0 0 
Pool 13: 0 0 0 0 0 0 0 0 
Pool 14: 0 0 0 0 0 0 0 0 
Pool 15: 0 0 0 0 0 0 0 0

Even with --enable-rss, the packets are still being placed in VLAN Pool 1/Queue 0 
instead of VLAN Pool 1/Queue 2.

As I mentioned in my original email, if I use an 82599ES (dual 10G NIC), it all
works as expected.

What am I missing?
--Mike

On 9/18/19, 7:54 AM, "Christensen, ChadX M" <chadx.m.christensen at intel.com> wrote:

    [EXTERNAL SENDER]
    
    Hi Mike,
    
    Did that resolve it?
    
    Thanks,
    
    Chad Christensen | Ecosystem Enablement Manager
    chadx.m.christensen at intel.com | (801) 786-5703
    
    -----Original Message-----
    From: Mike DeVico <mdevico at xcom-labs.com>
    Sent: Wednesday, September 18, 2019 8:17 AM
    To: Zhang, Xiao <xiao.zhang at intel.com>; Thomas Monjalon <thomas at monjalon.net>
    Cc: users at dpdk.org; Xing, Beilei <beilei.xing at intel.com>; Zhang, Qi Z <qi.z.zhang at intel.com>; Richardson, Bruce <bruce.richardson at intel.com>; Ananyev, Konstantin <konstantin.ananyev at intel.com>; Yigit, Ferruh <ferruh.yigit at intel.com>; Christensen, ChadX M <chadx.m.christensen at intel.com>; Tia Cassett <tiac at xcom-labs.com>; Wu, Jingjing <jingjing.wu at intel.com>; Wong1, Samuel <samuel.wong1 at intel.com>
    Subject: Re: [dpdk-dev] Issue with DCB with X710 Quad 10Gb NIC
    
    Sure enough, I see it now. I'll give it a try.
    
    Thanks!!!
    --Mike
    
    On 9/18/19, 12:11 AM, "Zhang, Xiao" <xiao.zhang at intel.com> wrote:
    
        [EXTERNAL SENDER]
    
        > -----Original Message-----
        > From: Thomas Monjalon [mailto:thomas at monjalon.net]
        > Sent: Wednesday, September 18, 2019 3:03 PM
        > To: Zhang, Xiao <xiao.zhang at intel.com>
        > Cc: Mike DeVico <mdevico at xcom-labs.com>; users at dpdk.org; Xing, Beilei
        > <beilei.xing at intel.com>; Zhang, Qi Z <qi.z.zhang at intel.com>; Richardson, Bruce
        > <bruce.richardson at intel.com>; Ananyev, Konstantin
        > <konstantin.ananyev at intel.com>; Yigit, Ferruh <ferruh.yigit at intel.com>;
        > Christensen, ChadX M <chadx.m.christensen at intel.com>; Tia Cassett
        > <tiac at xcom-labs.com>; Wu, Jingjing <jingjing.wu at intel.com>
        > Subject: Re: [dpdk-dev] Issue with DCB with X710 Quad 10Gb NIC
        >
        > 18/09/2019 09:02, Zhang, Xiao:
        > >
        > > There is some hardware limitation and need to enable RSS to distribute
        > packets for X710.
        >
        > Is this limitation documented?
    
        Yes, it's documented in doc/guides/nics/i40e.rst
    
        "DCB works only when RSS is enabled."
    
        >