[dpdk-dev] [PATCH] net/mlx5: add 128B padding of Rx completion entry

Shahaf Shuler shahafs at mellanox.com
Sun Oct 28 14:55:46 CET 2018

Thursday, October 25, 2018 9:24 AM, Yongseok Koh:
> Subject: [PATCH] net/mlx5: add 128B padding of Rx completion entry
> A PMD parameter (rxq_cqe_pad_en) is added to enable 128B padding of
> CQE on RX side. The size of CQE is aligned with the size of a cacheline of the
> core. If cacheline size is 128B, the CQE size is configured to be 128B even
> though the device writes only 64B data on the cacheline. This is to avoid
> unnecessary cache invalidation by device's two consecutive writes on to one
> cacheline. However in some architecture, it is more beneficial to update
> entire cacheline with padding the rest 64B rather than striding because read-
> modify-write could drop performance a lot. On the other hand, writing extra
> data will consume more PCIe bandwidth and could also drop the maximum
> throughput. It is recommended to empirically set this parameter. Disabled by
> default.
> Signed-off-by: Yongseok Koh <yskoh at mellanox.com>

Applied to next-net-mlx, thanks. 

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