[PATCH 1/2] common/cnxk: set CPT cache line size per platform

[Tejasree Kondoj]

From: Nithinsen Kaithakadan <nkaithakadan at marvell.com>

Added conditional definition for cache line size:
 - For CN10K and CN9k platform, set cache line size to 128 bytes.
 - For others, default to 256 bytes.

Signed-off-by: Nithinsen Kaithakadan <nkaithakadan at marvell.com>
---
 drivers/common/cnxk/roc_cpt.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 67956758be..37873820e2 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -130,7 +130,12 @@
 	 BITS_PER_LONG_LONG)
 
 /* ROC CPTR Cache */
+#if defined(ROC_PLATFORM_CN10K) || defined(ROC_PLATFORM_CN9K)
+#define ROC_CPTR_CACHE_LINE_SZ 128
+#else
 #define ROC_CPTR_CACHE_LINE_SZ 256
+#endif
+
 #define ROC_CPTR_ALIGN	       ROC_CPTR_CACHE_LINE_SZ
 
 #define ROC_CPT_CQ_ENTRY_SIZE_UNIT 32
-- 
2.25.1