|WARNING| [v2] config/arm: add Marvell CN20k

[dpdklab at iol.unh.edu]

Test-Label: ai-code-review
Test-Status: WARNING
https://dpdk.org/patch/172353

_AI Code Review_

=== Patch Review: series.patch (via Claude) ===
Review date: 2026-11-02

# Review of DPDK Patch: config/arm: add Marvell CN20k

## ERRORS

None identified.

## WARNINGS

### 1. Missing release notes update (Warning)

This patch adds support for a new SoC platform (Marvell CN20k) but does not include updates to the release notes. New platform support is a user-visible feature that should be documented in `doc/guides/rel_notes/release_25_03.rst` (or the appropriate current release file).

**Suggested fix:**
Add a release notes entry under "New Features" section:
```rst
* **Added support for Marvell OCTEON 20 (CN20k) platform.**

  Added ARM cross-compilation configuration for Marvell CN20k SoC based on
  ARM Neoverse N3 cores.
```

### 2. Asymmetric `RTE_MAX_LCORE` value (Warning)

The CN20k configuration sets `RTE_MAX_LCORE` to 42, which is an unusual value. Looking at other Marvell OCTEON platforms in the same file:
- `cn9k`: `RTE_MAX_LCORE` = 36
- `cn10k`: `RTE_MAX_LCORE` = 108

The value 42 seems arbitrary or possibly incorrect. If CN20k truly has 42 cores maximum, this is acceptable, but it warrants verification. If this is based on specific hardware constraints, consider adding a comment explaining the value.

**Suggested action:**
Verify that 42 is the correct maximum number of lcores for CN20k hardware. If unusual, add a comment explaining why this specific value is used.

## INFO

### Technical observations

1. **Part number**: The part number `0xd8e` (3470 decimal) corresponds to the ARM Neoverse N3 core as documented in ARM's specification, which is consistent with the commit message description.

2. **No crypto march feature**: Unlike `cobalt100` which sets `'extra_march_features': ['crypto']`, the CN20k configuration does not enable any extra march features. This is consistent with other Marvell OCTEON configs (`cn9k`, `cn10k`) which also do not set this field.

3. **Single NUMA node**: The configuration correctly sets both `'numa': false` in the soc definition and `'RTE_MAX_NUMA_NODES': 1` in flags, which is internally consistent.

4. **Cross-compilation file**: The new cross-compilation file follows the established pattern for other ARM platforms and is appropriately placed in `config/arm/`.

5. **Alphabetical ordering**: The new entries are correctly placed in alphabetical order in both the help text and the `socs` dictionary.

---

Review-Result: WARNING